diff options
Diffstat (limited to 'arch/arm/mach-davinci/dm644x.c')
| -rw-r--r-- | arch/arm/mach-davinci/dm644x.c | 442 |
1 files changed, 377 insertions, 65 deletions
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index fb5449b3c97..dc52657909c 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -8,19 +8,16 @@ * is licensed "as is" without any warranty of any kind, whether express * or implied. */ -#include <linux/kernel.h> #include <linux/init.h> #include <linux/clk.h> #include <linux/serial_8250.h> #include <linux/platform_device.h> -#include <linux/gpio.h> +#include <linux/platform_data/edma.h> +#include <linux/platform_data/gpio-davinci.h> #include <asm/mach/map.h> -#include <mach/dm644x.h> -#include <mach/clock.h> #include <mach/cputype.h> -#include <mach/edma.h> #include <mach/irqs.h> #include <mach/psc.h> #include <mach/mux.h> @@ -28,14 +25,23 @@ #include <mach/serial.h> #include <mach/common.h> +#include "davinci.h" #include "clock.h" #include "mux.h" +#include "asp.h" /* * Device specific clocks */ #define DM644X_REF_FREQ 27000000 +#define DM644X_EMAC_BASE 0x01c80000 +#define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000) +#define DM644X_EMAC_CNTRL_OFFSET 0x0000 +#define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000 +#define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000 +#define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000 + static struct pll_data pll1_data = { .num = 1, .phys_base = DAVINCI_PLL1_BASE, @@ -131,7 +137,7 @@ static struct clk dsp_clk = { .name = "dsp", .parent = &pll1_sysclk1, .lpsc = DAVINCI_LPSC_GEM, - .flags = PSC_DSP, + .domain = DAVINCI_GPSC_DSPDOMAIN, .usecount = 1, /* REVISIT how to disable? */ }; @@ -146,7 +152,7 @@ static struct clk vicp_clk = { .name = "vicp", .parent = &pll1_sysclk2, .lpsc = DAVINCI_LPSC_IMCOP, - .flags = PSC_DSP, + .domain = DAVINCI_GPSC_DSPDOMAIN, .usecount = 1, /* REVISIT how to disable? */ }; @@ -275,10 +281,10 @@ static struct clk timer2_clk = { .name = "timer2", .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_TIMER2, - .usecount = 1, /* REVISIT: why cant' this be disabled? */ + .usecount = 1, /* REVISIT: why can't this be disabled? */ }; -struct davinci_clk dm644x_clks[] = { +static struct clk_lookup dm644x_clks[] = { CLK(NULL, "ref", &ref_clk), CLK(NULL, "pll1", &pll1_clk), CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), @@ -294,17 +300,18 @@ struct davinci_clk dm644x_clks[] = { CLK(NULL, "dsp", &dsp_clk), CLK(NULL, "arm", &arm_clk), CLK(NULL, "vicp", &vicp_clk), - CLK(NULL, "vpss_master", &vpss_master_clk), - CLK(NULL, "vpss_slave", &vpss_slave_clk), + CLK("vpss", "master", &vpss_master_clk), + CLK("vpss", "slave", &vpss_slave_clk), CLK(NULL, "arm", &arm_clk), - CLK(NULL, "uart0", &uart0_clk), - CLK(NULL, "uart1", &uart1_clk), - CLK(NULL, "uart2", &uart2_clk), + CLK("serial8250.0", NULL, &uart0_clk), + CLK("serial8250.1", NULL, &uart1_clk), + CLK("serial8250.2", NULL, &uart2_clk), CLK("davinci_emac.1", NULL, &emac_clk), + CLK("davinci_mdio.0", "fck", &emac_clk), CLK("i2c_davinci.1", NULL, &i2c_clk), CLK("palm_bk3710", NULL, &ide_clk), - CLK("soc-audio.0", NULL, &asp_clk), - CLK("davinci_mmc.0", NULL, &mmcsd_clk), + CLK("davinci-mcbsp", NULL, &asp_clk), + CLK("dm6441-mmc.0", NULL, &mmcsd_clk), CLK(NULL, "spi", &spi_clk), CLK(NULL, "gpio", &gpio_clk), CLK(NULL, "usb", &usb_clk), @@ -315,7 +322,7 @@ struct davinci_clk dm644x_clks[] = { CLK(NULL, "pwm2", &pwm2_clk), CLK(NULL, "timer0", &timer0_clk), CLK(NULL, "timer1", &timer1_clk), - CLK("watchdog", NULL, &timer2_clk), + CLK("davinci-wdt", NULL, &timer2_clk), CLK(NULL, NULL, NULL), }; @@ -323,7 +330,6 @@ static struct emac_platform_data dm644x_emac_pdata = { .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET, .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET, .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET, - .mdio_reg_offset = DM644X_EMAC_MDIO_OFFSET, .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE, .version = EMAC_VERSION_1, }; @@ -331,7 +337,7 @@ static struct emac_platform_data dm644x_emac_pdata = { static struct resource dm644x_emac_resources[] = { { .start = DM644X_EMAC_BASE, - .end = DM644X_EMAC_BASE + 0x47ff, + .end = DM644X_EMAC_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, { @@ -351,8 +357,20 @@ static struct platform_device dm644x_emac_device = { .resource = dm644x_emac_resources, }; -#define PINMUX0 0x00 -#define PINMUX1 0x04 +static struct resource dm644x_mdio_resources[] = { + { + .start = DM644X_EMAC_MDIO_BASE, + .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm644x_mdio_device = { + .name = "davinci_mdio", + .id = 0, + .num_resources = ARRAY_SIZE(dm644x_mdio_resources), + .resource = dm644x_mdio_resources, +}; /* * Device specific mux setup @@ -369,6 +387,11 @@ MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true) MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true) MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true) +MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true) +MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true) +MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true) +MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true) +MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true) MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false) @@ -475,26 +498,26 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = { /*----------------------------------------------------------------------*/ -static const s8 dma_chan_dm644x_no_event[] = { - 0, 1, 12, 13, 14, - 15, 25, 30, 31, 45, - 46, 47, 55, 56, 57, - 58, 59, 60, 61, 62, - 63, - -1 +static s8 +queue_priority_mapping[][2] = { + /* {event queue no, Priority} */ + {0, 3}, + {1, 7}, + {-1, -1}, +}; + +static struct edma_soc_info edma_cc0_info = { + .queue_priority_mapping = queue_priority_mapping, + .default_queue = EVENTQ_1, }; -static struct edma_soc_info dm644x_edma_info = { - .n_channel = 64, - .n_region = 4, - .n_slot = 128, - .n_tc = 2, - .noevent = dma_chan_dm644x_no_event, +static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = { + &edma_cc0_info, }; static struct resource edma_resources[] = { { - .name = "edma_cc", + .name = "edma_cc0", .start = 0x01c00000, .end = 0x01c00000 + SZ_64K - 1, .flags = IORESOURCE_MEM, @@ -512,10 +535,12 @@ static struct resource edma_resources[] = { .flags = IORESOURCE_MEM, }, { + .name = "edma0", .start = IRQ_CCINT0, .flags = IORESOURCE_IRQ, }, { + .name = "edma0_err", .start = IRQ_CCERRINT, .flags = IORESOURCE_IRQ, }, @@ -524,12 +549,238 @@ static struct resource edma_resources[] = { static struct platform_device dm644x_edma_device = { .name = "edma", - .id = -1, - .dev.platform_data = &dm644x_edma_info, + .id = 0, + .dev.platform_data = dm644x_edma_info, .num_resources = ARRAY_SIZE(edma_resources), .resource = edma_resources, }; +/* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */ +static struct resource dm644x_asp_resources[] = { + { + .name = "mpu", + .start = DAVINCI_ASP0_BASE, + .end = DAVINCI_ASP0_BASE + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DAVINCI_DMA_ASP0_TX, + .end = DAVINCI_DMA_ASP0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = DAVINCI_DMA_ASP0_RX, + .end = DAVINCI_DMA_ASP0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device dm644x_asp_device = { + .name = "davinci-mcbsp", + .id = -1, + .num_resources = ARRAY_SIZE(dm644x_asp_resources), + .resource = dm644x_asp_resources, +}; + +#define DM644X_VPSS_BASE 0x01c73400 + +static struct resource dm644x_vpss_resources[] = { + { + /* VPSS Base address */ + .name = "vpss", + .start = DM644X_VPSS_BASE, + .end = DM644X_VPSS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm644x_vpss_device = { + .name = "vpss", + .id = -1, + .dev.platform_data = "dm644x_vpss", + .num_resources = ARRAY_SIZE(dm644x_vpss_resources), + .resource = dm644x_vpss_resources, +}; + +static struct resource dm644x_vpfe_resources[] = { + { + .start = IRQ_VDINT0, + .end = IRQ_VDINT0, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_VDINT1, + .end = IRQ_VDINT1, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32); +static struct resource dm644x_ccdc_resource[] = { + /* CCDC Base address */ + { + .start = 0x01c70400, + .end = 0x01c70400 + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm644x_ccdc_dev = { + .name = "dm644x_ccdc", + .id = -1, + .num_resources = ARRAY_SIZE(dm644x_ccdc_resource), + .resource = dm644x_ccdc_resource, + .dev = { + .dma_mask = &dm644x_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct platform_device dm644x_vpfe_dev = { + .name = CAPTURE_DRV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(dm644x_vpfe_resources), + .resource = dm644x_vpfe_resources, + .dev = { + .dma_mask = &dm644x_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +#define DM644X_OSD_BASE 0x01c72600 + +static struct resource dm644x_osd_resources[] = { + { + .start = DM644X_OSD_BASE, + .end = DM644X_OSD_BASE + 0x1ff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm644x_osd_dev = { + .name = DM644X_VPBE_OSD_SUBDEV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(dm644x_osd_resources), + .resource = dm644x_osd_resources, + .dev = { + .dma_mask = &dm644x_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +#define DM644X_VENC_BASE 0x01c72400 + +static struct resource dm644x_venc_resources[] = { + { + .start = DM644X_VENC_BASE, + .end = DM644X_VENC_BASE + 0x17f, + .flags = IORESOURCE_MEM, + }, +}; + +#define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0) +#define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1) +#define DM644X_VPSS_VENCLKEN BIT(3) +#define DM644X_VPSS_DACCLKEN BIT(4) + +static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type, + unsigned int pclock) +{ + int ret = 0; + u32 v = DM644X_VPSS_VENCLKEN; + + switch (type) { + case VPBE_ENC_STD: + v |= DM644X_VPSS_DACCLKEN; + writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); + break; + case VPBE_ENC_DV_TIMINGS: + if (pclock <= 27000000) { + v |= DM644X_VPSS_DACCLKEN; + writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); + } else { + /* + * For HD, use external clock source since + * HD requires higher clock rate + */ + v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE; + writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); + } + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static struct resource dm644x_v4l2_disp_resources[] = { + { + .start = IRQ_VENCINT, + .end = IRQ_VENCINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dm644x_vpbe_display = { + .name = "vpbe-v4l2", + .id = -1, + .num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources), + .resource = dm644x_v4l2_disp_resources, + .dev = { + .dma_mask = &dm644x_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct venc_platform_data dm644x_venc_pdata = { + .setup_clock = dm644x_venc_setup_clock, +}; + +static struct platform_device dm644x_venc_dev = { + .name = DM644X_VPBE_VENC_SUBDEV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(dm644x_venc_resources), + .resource = dm644x_venc_resources, + .dev = { + .dma_mask = &dm644x_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &dm644x_venc_pdata, + }, +}; + +static struct platform_device dm644x_vpbe_dev = { + .name = "vpbe_controller", + .id = -1, + .dev = { + .dma_mask = &dm644x_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource dm644_gpio_resources[] = { + { /* registers */ + .start = DAVINCI_GPIO_BASE, + .end = DAVINCI_GPIO_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { /* interrupt */ + .start = IRQ_GPIOBNK0, + .end = IRQ_GPIOBNK4, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct davinci_gpio_platform_data dm644_gpio_platform_data = { + .ngpio = 71, +}; + +int __init dm644x_gpio_register(void) +{ + return davinci_gpio_register(dm644_gpio_resources, + ARRAY_SIZE(dm644_gpio_resources), + &dm644_gpio_platform_data); +} /*----------------------------------------------------------------------*/ static struct map_desc dm644x_io_desc[] = { @@ -539,13 +790,6 @@ static struct map_desc dm644x_io_desc[] = { .length = IO_SIZE, .type = MT_DEVICE }, - { - .virtual = SRAM_VIRT, - .pfn = __phys_to_pfn(0x00008000), - .length = SZ_16K, - /* MT_MEMORY_NONCACHED requires supersection alignment */ - .type = MT_DEVICE, - }, }; /* Contents of JTAG ID register used to identify exact cpu type */ @@ -557,11 +801,16 @@ static struct davinci_id dm644x_ids[] = { .cpu_id = DAVINCI_CPU_ID_DM6446, .name = "dm6446", }, + { + .variant = 0x1, + .part_no = 0xb700, + .manufacturer = 0x017, + .cpu_id = DAVINCI_CPU_ID_DM6446, + .name = "dm6446a", + }, }; -static void __iomem *dm644x_psc_bases[] = { - IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), -}; +static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE }; /* * T0_BOT: Timer 0, bottom: clockevent source for hrtimers @@ -569,13 +818,13 @@ static void __iomem *dm644x_psc_bases[] = { * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) * T1_TOP: Timer 1, top : <unused> */ -struct davinci_timer_info dm644x_timer_info = { +static struct davinci_timer_info dm644x_timer_info = { .timers = davinci_timer_instance, .clockevent_id = T0_BOT, .clocksource_id = T0_TOP, }; -static struct plat_serial8250_port dm644x_serial_platform_data[] = { +static struct plat_serial8250_port dm644x_serial0_platform_data[] = { { .mapbase = DAVINCI_UART0_BASE, .irq = IRQ_UARTINT0, @@ -585,6 +834,11 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = { .regshift = 2, }, { + .flags = 0, + } +}; +static struct plat_serial8250_port dm644x_serial1_platform_data[] = { + { .mapbase = DAVINCI_UART1_BASE, .irq = IRQ_UARTINT1, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | @@ -593,6 +847,11 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = { .regshift = 2, }, { + .flags = 0, + } +}; +static struct plat_serial8250_port dm644x_serial2_platform_data[] = { + { .mapbase = DAVINCI_UART2_BASE, .irq = IRQ_UARTINT2, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | @@ -601,57 +860,110 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = { .regshift = 2, }, { - .flags = 0 - }, + .flags = 0, + } }; -static struct platform_device dm644x_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = dm644x_serial_platform_data, +struct platform_device dm644x_serial_device[] = { + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = dm644x_serial0_platform_data, + } + }, + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev = { + .platform_data = dm644x_serial1_platform_data, + } + }, + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, + .dev = { + .platform_data = dm644x_serial2_platform_data, + } }, + { + } }; static struct davinci_soc_info davinci_soc_info_dm644x = { .io_desc = dm644x_io_desc, .io_desc_num = ARRAY_SIZE(dm644x_io_desc), - .jtag_id_base = IO_ADDRESS(0x01c40028), + .jtag_id_reg = 0x01c40028, .ids = dm644x_ids, .ids_num = ARRAY_SIZE(dm644x_ids), .cpu_clks = dm644x_clks, .psc_bases = dm644x_psc_bases, .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases), - .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), + .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, .pinmux_pins = dm644x_pins, .pinmux_pins_num = ARRAY_SIZE(dm644x_pins), - .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), + .intc_base = DAVINCI_ARM_INTC_BASE, .intc_type = DAVINCI_INTC_TYPE_AINTC, .intc_irq_prios = dm644x_default_priorities, .intc_irq_num = DAVINCI_N_AINTC_IRQ, .timer_info = &dm644x_timer_info, - .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE), - .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), - .gpio_num = 71, - .gpio_irq = IRQ_GPIOBNK0, - .serial_dev = &dm644x_serial_device, .emac_pdata = &dm644x_emac_pdata, .sram_dma = 0x00008000, .sram_len = SZ_16K, }; +void __init dm644x_init_asp(struct snd_platform_data *pdata) +{ + davinci_cfg_reg(DM644X_MCBSP); + dm644x_asp_device.dev.platform_data = pdata; + platform_device_register(&dm644x_asp_device); +} + void __init dm644x_init(void) { davinci_common_init(&davinci_soc_info_dm644x); + davinci_map_sysmod(); +} + +int __init dm644x_init_video(struct vpfe_config *vpfe_cfg, + struct vpbe_config *vpbe_cfg) +{ + if (vpfe_cfg || vpbe_cfg) + platform_device_register(&dm644x_vpss_device); + + if (vpfe_cfg) { + dm644x_vpfe_dev.dev.platform_data = vpfe_cfg; + platform_device_register(&dm644x_ccdc_dev); + platform_device_register(&dm644x_vpfe_dev); + } + + if (vpbe_cfg) { + dm644x_vpbe_dev.dev.platform_data = vpbe_cfg; + platform_device_register(&dm644x_osd_dev); + platform_device_register(&dm644x_venc_dev); + platform_device_register(&dm644x_vpbe_dev); + platform_device_register(&dm644x_vpbe_display); + } + + return 0; } static int __init dm644x_init_devices(void) { + int ret = 0; + if (!cpu_is_davinci_dm644x()) return 0; platform_device_register(&dm644x_edma_device); + + platform_device_register(&dm644x_mdio_device); platform_device_register(&dm644x_emac_device); - return 0; + + ret = davinci_init_wdt(); + if (ret) + pr_warn("%s: watchdog init failed: %d\n", __func__, ret); + + return ret; } postcore_initcall(dm644x_init_devices); |