diff options
Diffstat (limited to 'arch/arm/mach-davinci/dm365.c')
| -rw-r--r-- | arch/arm/mach-davinci/dm365.c | 308 |
1 files changed, 247 insertions, 61 deletions
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 6c3980540be..0ae8114f5cc 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -18,20 +18,20 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/spi/spi.h> +#include <linux/platform_data/edma.h> +#include <linux/platform_data/gpio-davinci.h> +#include <linux/platform_data/keyscan-davinci.h> +#include <linux/platform_data/spi-davinci.h> #include <asm/mach/map.h> #include <mach/cputype.h> -#include <mach/edma.h> #include <mach/psc.h> #include <mach/mux.h> #include <mach/irqs.h> #include <mach/time.h> #include <mach/serial.h> #include <mach/common.h> -#include <linux/platform_data/keyscan-davinci.h> -#include <linux/platform_data/spi-davinci.h> -#include <mach/gpio-davinci.h> #include "davinci.h" #include "clock.h" @@ -39,16 +39,13 @@ #include "asp.h" #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ - -/* Base of key scan register bank */ -#define DM365_KEYSCAN_BASE 0x01c69400 - #define DM365_RTC_BASE 0x01c69000 - +#define DM365_KEYSCAN_BASE 0x01c69400 +#define DM365_OSD_BASE 0x01c71c00 +#define DM365_VENC_BASE 0x01c71e00 #define DAVINCI_DM365_VC_BASE 0x01d0c000 #define DAVINCI_DMA_VC_TX 2 #define DAVINCI_DMA_VC_RX 3 - #define DM365_EMAC_BASE 0x01d07000 #define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000) #define DM365_EMAC_CNTRL_OFFSET 0x0000 @@ -257,6 +254,12 @@ static struct clk vpss_master_clk = { .flags = CLK_PSC, }; +static struct clk vpss_slave_clk = { + .name = "vpss_slave", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_VPSSSLV, +}; + static struct clk arm_clk = { .name = "arm_clk", .parent = &pll2_sysclk2, @@ -449,13 +452,14 @@ static struct clk_lookup dm365_clks[] = { CLK(NULL, "pll2_sysclk8", &pll2_sysclk8), CLK(NULL, "pll2_sysclk9", &pll2_sysclk9), CLK(NULL, "vpss_dac", &vpss_dac_clk), - CLK(NULL, "vpss_master", &vpss_master_clk), + CLK("vpss", "master", &vpss_master_clk), + CLK("vpss", "slave", &vpss_slave_clk), CLK(NULL, "arm", &arm_clk), - CLK(NULL, "uart0", &uart0_clk), - CLK(NULL, "uart1", &uart1_clk), + CLK("serial8250.0", NULL, &uart0_clk), + CLK("serial8250.1", NULL, &uart1_clk), CLK("i2c_davinci.1", NULL, &i2c_clk), - CLK("davinci_mmc.0", NULL, &mmcsd0_clk), - CLK("davinci_mmc.1", NULL, &mmcsd1_clk), + CLK("da830-mmc.0", NULL, &mmcsd0_clk), + CLK("da830-mmc.1", NULL, &mmcsd1_clk), CLK("spi_davinci.0", NULL, &spi0_clk), CLK("spi_davinci.1", NULL, &spi1_clk), CLK("spi_davinci.2", NULL, &spi2_clk), @@ -469,10 +473,11 @@ static struct clk_lookup dm365_clks[] = { CLK(NULL, "pwm3", &pwm3_clk), CLK(NULL, "timer0", &timer0_clk), CLK(NULL, "timer1", &timer1_clk), - CLK("watchdog", NULL, &timer2_clk), + CLK("davinci-wdt", NULL, &timer2_clk), CLK(NULL, "timer3", &timer3_clk), CLK(NULL, "usb", &usb_clk), CLK("davinci_emac.1", NULL, &emac_clk), + CLK("davinci_mdio.0", "fck", &emac_clk), CLK("davinci_voicecodec", NULL, &voicecodec_clk), CLK("davinci-mcbsp", NULL, &asp0_clk), CLK(NULL, "rto", &rto_clk), @@ -693,6 +698,31 @@ void __init dm365_init_spi0(unsigned chipselect_mask, platform_device_register(&dm365_spi0_device); } +static struct resource dm365_gpio_resources[] = { + { /* registers */ + .start = DAVINCI_GPIO_BASE, + .end = DAVINCI_GPIO_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { /* interrupt */ + .start = IRQ_DM365_GPIO0, + .end = IRQ_DM365_GPIO7, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct davinci_gpio_platform_data dm365_gpio_platform_data = { + .ngpio = 104, + .gpio_unbanked = 8, +}; + +int __init dm365_gpio_register(void) +{ + return davinci_gpio_register(dm365_gpio_resources, + ARRAY_SIZE(dm365_gpio_resources), + &dm365_gpio_platform_data); +} + static struct emac_platform_data dm365_emac_pdata = { .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET, .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET, @@ -822,17 +852,7 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = { }; /* Four Transfer Controllers on DM365 */ -static const s8 -dm365_queue_tc_mapping[][2] = { - /* {event queue no, TC no} */ - {0, 0}, - {1, 1}, - {2, 2}, - {3, 3}, - {-1, -1}, -}; - -static const s8 +static s8 dm365_queue_priority_mapping[][2] = { /* {event queue no, Priority} */ {0, 7}, @@ -843,12 +863,6 @@ dm365_queue_priority_mapping[][2] = { }; static struct edma_soc_info edma_cc0_info = { - .n_channel = 64, - .n_region = 4, - .n_slot = 256, - .n_tc = 4, - .n_cc = 1, - .queue_tc_mapping = dm365_queue_tc_mapping, .queue_priority_mapping = dm365_queue_priority_mapping, .default_queue = EVENTQ_3, }; @@ -911,6 +925,7 @@ static struct platform_device dm365_edma_device = { static struct resource dm365_asp_resources[] = { { + .name = "mpu", .start = DAVINCI_DM365_ASP0_BASE, .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1, .flags = IORESOURCE_MEM, @@ -1037,7 +1052,7 @@ static struct davinci_timer_info dm365_timer_info = { #define DM365_UART1_BASE (IO_PHYS + 0x106000) -static struct plat_serial8250_port dm365_serial_platform_data[] = { +static struct plat_serial8250_port dm365_serial0_platform_data[] = { { .mapbase = DAVINCI_UART0_BASE, .irq = IRQ_UARTINT0, @@ -1047,6 +1062,11 @@ static struct plat_serial8250_port dm365_serial_platform_data[] = { .regshift = 2, }, { + .flags = 0, + } +}; +static struct plat_serial8250_port dm365_serial1_platform_data[] = { + { .mapbase = DM365_UART1_BASE, .irq = IRQ_UARTINT1, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | @@ -1055,16 +1075,27 @@ static struct plat_serial8250_port dm365_serial_platform_data[] = { .regshift = 2, }, { - .flags = 0 - }, + .flags = 0, + } }; -static struct platform_device dm365_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = dm365_serial_platform_data, +struct platform_device dm365_serial_device[] = { + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = dm365_serial0_platform_data, + } }, + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev = { + .platform_data = dm365_serial1_platform_data, + } + }, + { + } }; static struct davinci_soc_info davinci_soc_info_dm365 = { @@ -1084,12 +1115,6 @@ static struct davinci_soc_info davinci_soc_info_dm365 = { .intc_irq_prios = dm365_default_priorities, .intc_irq_num = DAVINCI_N_AINTC_IRQ, .timer_info = &dm365_timer_info, - .gpio_type = GPIO_TYPE_DAVINCI, - .gpio_base = DAVINCI_GPIO_BASE, - .gpio_num = 104, - .gpio_irq = IRQ_DM365_GPIO0, - .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */ - .serial_dev = &dm365_serial_device, .emac_pdata = &dm365_emac_pdata, .sram_dma = 0x00010000, .sram_len = SZ_32K, @@ -1226,8 +1251,177 @@ static struct platform_device dm365_isif_dev = { }, }; +static struct resource dm365_osd_resources[] = { + { + .start = DM365_OSD_BASE, + .end = DM365_OSD_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static u64 dm365_video_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device dm365_osd_dev = { + .name = DM365_VPBE_OSD_SUBDEV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(dm365_osd_resources), + .resource = dm365_osd_resources, + .dev = { + .dma_mask = &dm365_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource dm365_venc_resources[] = { + { + .start = IRQ_VENCINT, + .end = IRQ_VENCINT, + .flags = IORESOURCE_IRQ, + }, + /* venc registers io space */ + { + .start = DM365_VENC_BASE, + .end = DM365_VENC_BASE + 0x177, + .flags = IORESOURCE_MEM, + }, + /* vdaccfg registers io space */ + { + .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG, + .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource dm365_v4l2_disp_resources[] = { + { + .start = IRQ_VENCINT, + .end = IRQ_VENCINT, + .flags = IORESOURCE_IRQ, + }, + /* venc registers io space */ + { + .start = DM365_VENC_BASE, + .end = DM365_VENC_BASE + 0x177, + .flags = IORESOURCE_MEM, + }, +}; + +static int dm365_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type, + int field) +{ + switch (if_type) { + case V4L2_MBUS_FMT_SGRBG8_1X8: + davinci_cfg_reg(DM365_VOUT_FIELD_G81); + davinci_cfg_reg(DM365_VOUT_COUTL_EN); + davinci_cfg_reg(DM365_VOUT_COUTH_EN); + break; + case V4L2_MBUS_FMT_YUYV10_1X20: + if (field) + davinci_cfg_reg(DM365_VOUT_FIELD); + else + davinci_cfg_reg(DM365_VOUT_FIELD_G81); + davinci_cfg_reg(DM365_VOUT_COUTL_EN); + davinci_cfg_reg(DM365_VOUT_COUTH_EN); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type, + unsigned int pclock) +{ + void __iomem *vpss_clkctl_reg; + u32 val; + + vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL); + + switch (type) { + case VPBE_ENC_STD: + val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE; + break; + case VPBE_ENC_DV_TIMINGS: + if (pclock <= 27000000) { + val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE; + } else { + /* set sysclk4 to output 74.25 MHz from pll1 */ + val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE | + VPSS_VENCCLKEN_ENABLE; + } + break; + default: + return -EINVAL; + } + writel(val, vpss_clkctl_reg); + + return 0; +} + +static struct platform_device dm365_vpbe_display = { + .name = "vpbe-v4l2", + .id = -1, + .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources), + .resource = dm365_v4l2_disp_resources, + .dev = { + .dma_mask = &dm365_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct venc_platform_data dm365_venc_pdata = { + .setup_pinmux = dm365_vpbe_setup_pinmux, + .setup_clock = dm365_venc_setup_clock, +}; + +static struct platform_device dm365_venc_dev = { + .name = DM365_VPBE_VENC_SUBDEV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(dm365_venc_resources), + .resource = dm365_venc_resources, + .dev = { + .dma_mask = &dm365_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = (void *)&dm365_venc_pdata, + }, +}; + +static struct platform_device dm365_vpbe_dev = { + .name = "vpbe_controller", + .id = -1, + .dev = { + .dma_mask = &dm365_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +int __init dm365_init_video(struct vpfe_config *vpfe_cfg, + struct vpbe_config *vpbe_cfg) +{ + if (vpfe_cfg || vpbe_cfg) + platform_device_register(&dm365_vpss_device); + + if (vpfe_cfg) { + vpfe_capture_dev.dev.platform_data = vpfe_cfg; + platform_device_register(&dm365_isif_dev); + platform_device_register(&vpfe_capture_dev); + } + if (vpbe_cfg) { + dm365_vpbe_dev.dev.platform_data = vpbe_cfg; + platform_device_register(&dm365_osd_dev); + platform_device_register(&dm365_venc_dev); + platform_device_register(&dm365_vpbe_dev); + platform_device_register(&dm365_vpbe_display); + } + + return 0; +} + static int __init dm365_init_devices(void) { + int ret = 0; + if (!cpu_is_davinci_dm365()) return 0; @@ -1236,19 +1430,11 @@ static int __init dm365_init_devices(void) platform_device_register(&dm365_mdio_device); platform_device_register(&dm365_emac_device); - clk_add_alias(NULL, dev_name(&dm365_mdio_device.dev), - NULL, &dm365_emac_device.dev); - - /* Add isif clock alias */ - clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL); - platform_device_register(&dm365_vpss_device); - platform_device_register(&dm365_isif_dev); - platform_device_register(&vpfe_capture_dev); - return 0; -} -postcore_initcall(dm365_init_devices); -void dm365_set_vpfe_config(struct vpfe_config *cfg) -{ - vpfe_capture_dev.dev.platform_data = cfg; + ret = davinci_init_wdt(); + if (ret) + pr_warn("%s: watchdog init failed: %d\n", __func__, ret); + + return ret; } +postcore_initcall(dm365_init_devices); |