diff options
Diffstat (limited to 'arch/arm/mach-davinci/dm355.c')
| -rw-r--r-- | arch/arm/mach-davinci/dm355.c | 325 |
1 files changed, 252 insertions, 73 deletions
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 9be261beae7..2f3ed3a58d5 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -13,28 +13,29 @@ #include <linux/serial_8250.h> #include <linux/platform_device.h> #include <linux/dma-mapping.h> -#include <linux/gpio.h> - #include <linux/spi/spi.h> +#include <linux/platform_data/edma.h> +#include <linux/platform_data/gpio-davinci.h> +#include <linux/platform_data/spi-davinci.h> #include <asm/mach/map.h> -#include <mach/dm355.h> #include <mach/cputype.h> -#include <mach/edma.h> #include <mach/psc.h> #include <mach/mux.h> #include <mach/irqs.h> #include <mach/time.h> #include <mach/serial.h> #include <mach/common.h> -#include <mach/asp.h> -#include <mach/spi.h> +#include "davinci.h" #include "clock.h" #include "mux.h" +#include "asp.h" #define DM355_UART2_BASE (IO_PHYS + 0x206000) +#define DM355_OSD_BASE (IO_PHYS + 0x70200) +#define DM355_VENC_BASE (IO_PHYS + 0x70400) /* * Device specific clocks @@ -314,7 +315,7 @@ static struct clk timer2_clk = { .name = "timer2", .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_TIMER2, - .usecount = 1, /* REVISIT: why cant' this be disabled? */ + .usecount = 1, /* REVISIT: why can't this be disabled? */ }; static struct clk timer3_clk = { @@ -345,8 +346,8 @@ static struct clk_lookup dm355_clks[] = { CLK(NULL, "pll1_aux", &pll1_aux_clk), CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), CLK(NULL, "vpss_dac", &vpss_dac_clk), - CLK(NULL, "vpss_master", &vpss_master_clk), - CLK(NULL, "vpss_slave", &vpss_slave_clk), + CLK("vpss", "master", &vpss_master_clk), + CLK("vpss", "slave", &vpss_slave_clk), CLK(NULL, "clkout1", &clkout1_clk), CLK(NULL, "clkout2", &clkout2_clk), CLK(NULL, "pll2", &pll2_clk), @@ -355,14 +356,14 @@ static struct clk_lookup dm355_clks[] = { CLK(NULL, "clkout3", &clkout3_clk), CLK(NULL, "arm", &arm_clk), CLK(NULL, "mjcp", &mjcp_clk), - CLK(NULL, "uart0", &uart0_clk), - CLK(NULL, "uart1", &uart1_clk), - CLK(NULL, "uart2", &uart2_clk), + CLK("serial8250.0", NULL, &uart0_clk), + CLK("serial8250.1", NULL, &uart1_clk), + CLK("serial8250.2", NULL, &uart2_clk), CLK("i2c_davinci.1", NULL, &i2c_clk), - CLK("davinci-asp.0", NULL, &asp0_clk), - CLK("davinci-asp.1", NULL, &asp1_clk), - CLK("davinci_mmc.0", NULL, &mmcsd0_clk), - CLK("davinci_mmc.1", NULL, &mmcsd1_clk), + CLK("davinci-mcbsp.0", NULL, &asp0_clk), + CLK("davinci-mcbsp.1", NULL, &asp1_clk), + CLK("dm6441-mmc.0", NULL, &mmcsd0_clk), + CLK("dm6441-mmc.1", NULL, &mmcsd1_clk), CLK("spi_davinci.0", NULL, &spi0_clk), CLK("spi_davinci.1", NULL, &spi1_clk), CLK("spi_davinci.2", NULL, &spi2_clk), @@ -374,7 +375,7 @@ static struct clk_lookup dm355_clks[] = { CLK(NULL, "pwm3", &pwm3_clk), CLK(NULL, "timer0", &timer0_clk), CLK(NULL, "timer1", &timer1_clk), - CLK("watchdog", NULL, &timer2_clk), + CLK("davinci-wdt", NULL, &timer2_clk), CLK(NULL, "timer3", &timer3_clk), CLK(NULL, "rto", &rto_clk), CLK(NULL, "usb", &usb_clk), @@ -403,21 +404,13 @@ static struct resource dm355_spi0_resources[] = { .start = 16, .flags = IORESOURCE_DMA, }, - { - .start = EVENTQ_1, - .flags = IORESOURCE_DMA, - }, }; static struct davinci_spi_platform_data dm355_spi0_pdata = { .version = SPI_VERSION_1, .num_chipselect = 2, - .clk_internal = 1, - .cs_hold = 1, - .intr_level = 0, - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ - .c2tdelay = 0, - .t2cdelay = 0, + .cshold_bug = true, + .dma_event_q = EVENTQ_1, }; static struct platform_device dm355_spi0_device = { .name = "spi_davinci", @@ -432,7 +425,7 @@ static struct platform_device dm355_spi0_device = { }; void __init dm355_init_spi0(unsigned chipselect_mask, - struct spi_board_info *info, unsigned len) + const struct spi_board_info *info, unsigned len) { /* for now, assume we need MISO */ davinci_cfg_reg(DM355_SPI0_SDI); @@ -575,15 +568,7 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = { /*----------------------------------------------------------------------*/ -static const s8 -queue_tc_mapping[][2] = { - /* {event queue no, TC no} */ - {0, 0}, - {1, 1}, - {-1, -1}, -}; - -static const s8 +static s8 queue_priority_mapping[][2] = { /* {event queue no, Priority} */ {0, 3}, @@ -592,13 +577,8 @@ queue_priority_mapping[][2] = { }; static struct edma_soc_info edma_cc0_info = { - .n_channel = 64, - .n_region = 4, - .n_slot = 128, - .n_tc = 2, - .n_cc = 1, - .queue_tc_mapping = queue_tc_mapping, .queue_priority_mapping = queue_priority_mapping, + .default_queue = EVENTQ_1, }; static struct edma_soc_info *dm355_edma_info[EDMA_MAX_CC] = { @@ -647,6 +627,7 @@ static struct platform_device dm355_edma_device = { static struct resource dm355_asp1_resources[] = { { + .name = "mpu", .start = DAVINCI_ASP1_BASE, .end = DAVINCI_ASP1_BASE + SZ_8K - 1, .flags = IORESOURCE_MEM, @@ -664,7 +645,7 @@ static struct resource dm355_asp1_resources[] = { }; static struct platform_device dm355_asp1_device = { - .name = "davinci-asp", + .name = "davinci-mcbsp", .id = 1, .num_resources = ARRAY_SIZE(dm355_asp1_resources), .resource = dm355_asp1_resources, @@ -751,11 +732,169 @@ static struct platform_device vpfe_capture_dev = { }, }; -void dm355_set_vpfe_config(struct vpfe_config *cfg) +static struct resource dm355_osd_resources[] = { + { + .start = DM355_OSD_BASE, + .end = DM355_OSD_BASE + 0x17f, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm355_osd_dev = { + .name = DM355_VPBE_OSD_SUBDEV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(dm355_osd_resources), + .resource = dm355_osd_resources, + .dev = { + .dma_mask = &vpfe_capture_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource dm355_venc_resources[] = { + { + .start = IRQ_VENCINT, + .end = IRQ_VENCINT, + .flags = IORESOURCE_IRQ, + }, + /* venc registers io space */ + { + .start = DM355_VENC_BASE, + .end = DM355_VENC_BASE + 0x17f, + .flags = IORESOURCE_MEM, + }, + /* VDAC config register io space */ + { + .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG, + .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource dm355_v4l2_disp_resources[] = { + { + .start = IRQ_VENCINT, + .end = IRQ_VENCINT, + .flags = IORESOURCE_IRQ, + }, + /* venc registers io space */ + { + .start = DM355_VENC_BASE, + .end = DM355_VENC_BASE + 0x17f, + .flags = IORESOURCE_MEM, + }, +}; + +static int dm355_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type, + int field) +{ + switch (if_type) { + case V4L2_MBUS_FMT_SGRBG8_1X8: + davinci_cfg_reg(DM355_VOUT_FIELD_G70); + break; + case V4L2_MBUS_FMT_YUYV10_1X20: + if (field) + davinci_cfg_reg(DM355_VOUT_FIELD); + else + davinci_cfg_reg(DM355_VOUT_FIELD_G70); + break; + default: + return -EINVAL; + } + + davinci_cfg_reg(DM355_VOUT_COUTL_EN); + davinci_cfg_reg(DM355_VOUT_COUTH_EN); + + return 0; +} + +static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type, + unsigned int pclock) { - vpfe_capture_dev.dev.platform_data = cfg; + void __iomem *vpss_clk_ctrl_reg; + + vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL); + + switch (type) { + case VPBE_ENC_STD: + writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE, + vpss_clk_ctrl_reg); + break; + case VPBE_ENC_DV_TIMINGS: + if (pclock > 27000000) + /* + * For HD, use external clock source since we cannot + * support HD mode with internal clocks. + */ + writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg); + break; + default: + return -EINVAL; + } + + return 0; } +static struct platform_device dm355_vpbe_display = { + .name = "vpbe-v4l2", + .id = -1, + .num_resources = ARRAY_SIZE(dm355_v4l2_disp_resources), + .resource = dm355_v4l2_disp_resources, + .dev = { + .dma_mask = &vpfe_capture_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct venc_platform_data dm355_venc_pdata = { + .setup_pinmux = dm355_vpbe_setup_pinmux, + .setup_clock = dm355_venc_setup_clock, +}; + +static struct platform_device dm355_venc_dev = { + .name = DM355_VPBE_VENC_SUBDEV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(dm355_venc_resources), + .resource = dm355_venc_resources, + .dev = { + .dma_mask = &vpfe_capture_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = (void *)&dm355_venc_pdata, + }, +}; + +static struct platform_device dm355_vpbe_dev = { + .name = "vpbe_controller", + .id = -1, + .dev = { + .dma_mask = &vpfe_capture_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource dm355_gpio_resources[] = { + { /* registers */ + .start = DAVINCI_GPIO_BASE, + .end = DAVINCI_GPIO_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { /* interrupt */ + .start = IRQ_DM355_GPIOBNK0, + .end = IRQ_DM355_GPIOBNK6, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct davinci_gpio_platform_data dm355_gpio_platform_data = { + .ngpio = 104, +}; + +int __init dm355_gpio_register(void) +{ + return davinci_gpio_register(dm355_gpio_resources, + ARRAY_SIZE(dm355_gpio_resources), + &dm355_gpio_platform_data); +} /*----------------------------------------------------------------------*/ static struct map_desc dm355_io_desc[] = { @@ -765,12 +904,6 @@ static struct map_desc dm355_io_desc[] = { .length = IO_SIZE, .type = MT_DEVICE }, - { - .virtual = SRAM_VIRT, - .pfn = __phys_to_pfn(0x00010000), - .length = SZ_32K, - .type = MT_MEMORY_NONCACHED, - }, }; /* Contents of JTAG ID register used to identify exact cpu type */ @@ -798,7 +931,7 @@ static struct davinci_timer_info dm355_timer_info = { .clocksource_id = T0_TOP, }; -static struct plat_serial8250_port dm355_serial_platform_data[] = { +static struct plat_serial8250_port dm355_serial0_platform_data[] = { { .mapbase = DAVINCI_UART0_BASE, .irq = IRQ_UARTINT0, @@ -808,6 +941,11 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = { .regshift = 2, }, { + .flags = 0, + } +}; +static struct plat_serial8250_port dm355_serial1_platform_data[] = { + { .mapbase = DAVINCI_UART1_BASE, .irq = IRQ_UARTINT1, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | @@ -816,6 +954,11 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = { .regshift = 2, }, { + .flags = 0, + } +}; +static struct plat_serial8250_port dm355_serial2_platform_data[] = { + { .mapbase = DM355_UART2_BASE, .irq = IRQ_DM355_UARTINT2, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | @@ -824,16 +967,34 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = { .regshift = 2, }, { - .flags = 0 - }, + .flags = 0, + } }; -static struct platform_device dm355_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = dm355_serial_platform_data, +struct platform_device dm355_serial_device[] = { + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = dm355_serial0_platform_data, + } + }, + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev = { + .platform_data = dm355_serial1_platform_data, + } }, + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, + .dev = { + .platform_data = dm355_serial2_platform_data, + } + }, + { + } }; static struct davinci_soc_info davinci_soc_info_dm355 = { @@ -853,14 +1014,8 @@ static struct davinci_soc_info davinci_soc_info_dm355 = { .intc_irq_prios = dm355_default_priorities, .intc_irq_num = DAVINCI_N_AINTC_IRQ, .timer_info = &dm355_timer_info, - .gpio_type = GPIO_TYPE_DAVINCI, - .gpio_base = DAVINCI_GPIO_BASE, - .gpio_num = 104, - .gpio_irq = IRQ_DM355_GPIOBNK0, - .serial_dev = &dm355_serial_device, .sram_dma = 0x00010000, .sram_len = SZ_32K, - .reset_device = &davinci_wdt_device, }; void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata) @@ -879,22 +1034,46 @@ void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata) void __init dm355_init(void) { davinci_common_init(&davinci_soc_info_dm355); + davinci_map_sysmod(); +} + +int __init dm355_init_video(struct vpfe_config *vpfe_cfg, + struct vpbe_config *vpbe_cfg) +{ + if (vpfe_cfg || vpbe_cfg) + platform_device_register(&dm355_vpss_device); + + if (vpfe_cfg) { + vpfe_capture_dev.dev.platform_data = vpfe_cfg; + platform_device_register(&dm355_ccdc_dev); + platform_device_register(&vpfe_capture_dev); + } + + if (vpbe_cfg) { + dm355_vpbe_dev.dev.platform_data = vpbe_cfg; + platform_device_register(&dm355_osd_dev); + platform_device_register(&dm355_venc_dev); + platform_device_register(&dm355_vpbe_dev); + platform_device_register(&dm355_vpbe_display); + } + + return 0; } static int __init dm355_init_devices(void) { + int ret = 0; + if (!cpu_is_davinci_dm355()) return 0; - /* Add ccdc clock aliases */ - clk_add_alias("master", dm355_ccdc_dev.name, "vpss_master", NULL); - clk_add_alias("slave", dm355_ccdc_dev.name, "vpss_master", NULL); davinci_cfg_reg(DM355_INT_EDMA_CC); platform_device_register(&dm355_edma_device); - platform_device_register(&dm355_vpss_device); - platform_device_register(&dm355_ccdc_dev); - platform_device_register(&vpfe_capture_dev); - return 0; + ret = davinci_init_wdt(); + if (ret) + pr_warn("%s: watchdog init failed: %d\n", __func__, ret); + + return ret; } postcore_initcall(dm355_init_devices); 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