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-rw-r--r--arch/arm/include/asm/cache.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 66c160b8547..75fe66bc02b 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -14,7 +14,7 @@
* cache before the transfer is done, causing old data to be seen by
* the CPU.
*/
-#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
+#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/*
* With EABI on ARMv5 and above we must have 64-bit aligned slab pointers.
@@ -23,4 +23,6 @@
#define ARCH_SLAB_MINALIGN 8
#endif
+#define __read_mostly __attribute__((__section__(".data..read_mostly")))
+
#endif