diff options
Diffstat (limited to 'arch/arm/boot/dts/armada-xp-db.dts')
| -rw-r--r-- | arch/arm/boot/dts/armada-xp-db.dts | 200 |
1 files changed, 152 insertions, 48 deletions
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index 8e53b25b550..42ddb286436 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -2,7 +2,7 @@ * Device Tree file for Marvell Armada XP evaluation board * (DB-78460-BP) * - * Copyright (C) 2012 Marvell + * Copyright (C) 2012-2014 Marvell * * Lior Amsalem <alior@marvell.com> * Gregory CLEMENT <gregory.clement@free-electrons.com> @@ -11,10 +11,19 @@ * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. */ /dts-v1/; -/include/ "armada-xp-mv78460.dtsi" +#include "armada-xp-mv78460.dtsi" / { model = "Marvell Armada XP Evaluation Board"; @@ -26,69 +35,164 @@ memory { device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2 GB */ + reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ }; soc { - serial@d0012000 { - clock-frequency = <250000000>; - status = "okay"; - }; - serial@d0012100 { - clock-frequency = <250000000>; - status = "okay"; - }; - serial@d0012200 { - clock-frequency = <250000000>; - status = "okay"; - }; - serial@d0012300 { - clock-frequency = <250000000>; + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 + MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; + + devbus-bootcs { status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 16 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x1000000>; + bank-width = <2>; + }; }; - sata@d00a0000 { - nr-ports = <2>; + pcie-controller { status = "okay"; + + /* + * All 6 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + pcie@3,0 { + /* Port 0, Lane 2 */ + status = "okay"; + }; + pcie@4,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@10,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; }; - mdio { - phy0: ethernet-phy@0 { - reg = <0>; + internal-regs { + serial@12000 { + status = "okay"; + }; + serial@12100 { + status = "okay"; + }; + serial@12200 { + status = "okay"; + }; + serial@12300 { + status = "okay"; + }; + + sata@a0000 { + nr-ports = <2>; + status = "okay"; }; - phy1: ethernet-phy@1 { - reg = <1>; + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <25>; + }; + + phy3: ethernet-phy@3 { + reg = <27>; + }; }; - phy2: ethernet-phy@2 { - reg = <25>; + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + ethernet@30000 { + status = "okay"; + phy = <&phy2>; + phy-mode = "sgmii"; + }; + ethernet@34000 { + status = "okay"; + phy = <&phy3>; + phy-mode = "sgmii"; }; - phy3: ethernet-phy@3 { - reg = <27>; + mvsdio@d4000 { + pinctrl-0 = <&sdio_pins>; + pinctrl-names = "default"; + status = "okay"; + /* No CD or WP GPIOs */ + broken-cd; }; - }; - ethernet@d0070000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - ethernet@d0074000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - ethernet@d0030000 { - status = "okay"; - phy = <&phy2>; - phy-mode = "sgmii"; - }; - ethernet@d0034000 { - status = "okay"; - phy = <&phy3>; - phy-mode = "sgmii"; + usb@50000 { + status = "okay"; + }; + + usb@51000 { + status = "okay"; + }; + + usb@52000 { + status = "okay"; + }; + + spi0: spi@10600 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p64"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + }; + }; }; }; }; |