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| author | Rafał Miłecki <zajec5@gmail.com> | 2014-05-16 11:10:29 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2014-06-02 10:25:04 -0400 |
| commit | 2e93cac90c4b063c8732deb727a192dea1119640 (patch) | |
| tree | d693edcb5a2ae13673e194f2985bf8b417f1d2d3 /tools/perf/scripts/python/syscall-counts.py | |
| parent | 8f33a156c2adeddb5b5755b277b2c0b68da56ae2 (diff) | |
drm/radeon/hdmi: DCE3: clean ACR control
What initially seemed to be a typo in fglrx (using register 0x740c
instead of 0x74dc) appeared to be a correct behavior. DCE3 has ACR and
CRC registers swapped which explains why we needed
WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
This has been tested for possible regressions on DCE3 HD3470 (RV620).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions