diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-04-09 13:29:03 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-05-20 15:52:38 +0200 |
| commit | f72df8dbe2211cf2b70e54f8e9408b889fa56974 (patch) | |
| tree | fc8900ccbbd5ab19e78a79ea7edd426d4ede33f0 /tools/perf/scripts/python/sched-migration.py | |
| parent | 97fd4d5c81af7976b4ec9971a93bf3c361066c65 (diff) | |
drm/i915/chv: Don't do group access reads from TX lanes either
Like PCS, TX group reads return 0xffffffff. So we need to target each
lane separately if we want to use RMW cycles to update the registers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions