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| author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2014-01-23 18:41:10 -0800 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-02-03 12:41:37 +0000 |
| commit | 28dc4b63cdb96f2448a677320fcc0eb112e13e3f (patch) | |
| tree | 3cf5e71537e640c426db51206a9864bc0f875279 /tools/perf/scripts/python/netdev-times.py | |
| parent | 96c7c0d6f8c6e09e9123f0518130c047c5de40f6 (diff) | |
ASoC: rsnd: merge SRC clock timing/setting
SRC clock and timing setting register
exist in SRU and ADG on Gen1.
But, these are merged into ADG on Gen2.
Current driver is supporting Gen1 SRC only
at this point, but, above settings are
set as different function.
This patch merges these as preparation of Gen2 support.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions