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| author | Ben Skeggs <bskeggs@redhat.com> | 2013-11-04 11:00:59 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2013-11-08 15:39:55 +1000 |
| commit | 6d8d163132d7df6ca701efcde7832046ecb2f040 (patch) | |
| tree | a1ad9c04530d81f85b67198f190957ae0f981290 /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | d7b023d87a900fa80802e35aa0afbb3d60e808dc (diff) | |
drm/nvd0-/disp: reorder writes to lane current control regs
Matches the nv94-nvc0 commit with the same title. Doesn't fix a reported issue,
but NVIDIA use this ordering here too, so let's do it just in case.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions