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authorBen Widawsky <ben@bwidawsk.net>2012-11-26 21:52:54 -0800
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-11-29 11:14:44 +0100
commit2ff4aeac39dbdcac934694413767f09a27965e11 (patch)
treef2d45a27305cedd498819034f96fbcf06d1c111d /ipc/syscall.c
parent70b12bb415463c1bd146b67c5fbf6784fd046ad9 (diff)
drm/i915: Fix pte updates in ggtt clear range
This bug was introduced by me: commit e76e9aebcdbfebae8f4cd147e3c0f800d36e97f3 Author: Ben Widawsky <ben@bwidawsk.net> Date: Sun Nov 4 09:21:27 2012 -0800 drm/i915: Stop using AGP layer for GEN6+ The existing code uses memset_io which follows memset semantics in only guaranteeing a write of individual bytes. Since a PTE entry is 4 bytes, this can only be correct if the scratch page address is 0. This caused unsightly errors when we clear the range at load time, though I'm not really sure what the heck is referencing that memory anyway. I caught this is because I believe we have some other bug where the display is doing reads of memory we feel should be cleared (or we are relying on scratch pages to be a specific value). Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'ipc/syscall.c')
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