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| author | Dmitry Torokhov <dtor@insightbb.com> | 2006-12-08 01:07:56 -0500 |
|---|---|---|
| committer | Dmitry Torokhov <dtor@insightbb.com> | 2006-12-08 01:07:56 -0500 |
| commit | bef986502fa398b1785a3979b1aa17cd902d3527 (patch) | |
| tree | b59c1afe7b1dfcc001b86e54863f550d7ddc8c34 /include/asm-sh/cpu-sh2/cache.h | |
| parent | 4bdbd2807deeccc0793d57fb5120d7a53f2c0b3c (diff) | |
| parent | c99767974ebd2a719d849fdeaaa1674456f5283f (diff) | |
Merge rsync://rsync.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts:
drivers/usb/input/hid.h
Diffstat (limited to 'include/asm-sh/cpu-sh2/cache.h')
| -rw-r--r-- | include/asm-sh/cpu-sh2/cache.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h index cd96402e856..20b9796842d 100644 --- a/include/asm-sh/cpu-sh2/cache.h +++ b/include/asm-sh/cpu-sh2/cache.h @@ -12,6 +12,7 @@ #define L1_CACHE_SHIFT 4 +#if defined(CONFIG_CPU_SUBTYPE_SH7604) #define CCR 0xfffffe92 /* Address of Cache Control Register */ #define CCR_CACHE_CE 0x01 /* Cache enable */ @@ -27,5 +28,26 @@ #define CCR_CACHE_ORA CCR_CACHE_TW #define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */ +#elif defined(CONFIG_CPU_SUBTYPE_SH7619) +#define CCR1 0xffffffec +#define CCR CCR1 + +#define CCR_CACHE_CE 0x01 /* Cache enable */ +#define CCR_CACHE_WT 0x06 /* CCR[bit1=1,bit2=1] */ + /* 0x00000000-0x7fffffff: Write-through */ + /* 0x80000000-0x9fffffff: Write-back */ + /* 0xc0000000-0xdfffffff: Write-through */ +#define CCR_CACHE_CB 0x00 /* CCR[bit1=0,bit2=0] */ + /* 0x00000000-0x7fffffff: Write-back */ + /* 0x80000000-0x9fffffff: Write-through */ + /* 0xc0000000-0xdfffffff: Write-back */ +#define CCR_CACHE_CF 0x08 /* Cache invalidate */ + +#define CACHE_OC_ADDRESS_ARRAY 0xf0000000 +#define CACHE_OC_DATA_ARRAY 0xf1000000 + +#define CCR_CACHE_ENABLE CCR_CACHE_CE +#define CCR_CACHE_INVALIDATE CCR_CACHE_CF +#endif #endif /* __ASM_CPU_SH2_CACHE_H */ |