Staging: heci: fix setting h_is bit in h_csr register

Host software could issue interrupts to ME firmware, using H_IG bit. While
Setting H_IG bit, host software should preserve all the other bits in H_CSR
unchanged. In the original function which sets H_CSR register, they first read
the register, then set some bits, and write the whole 32bits back to the
register. And that the special behavior of H_IS (write-one-to-zero) causes problem.
This patch fixes the issue in the following ways:

 - Modify heci_set_csr_register() function so that it doesn't change H_IS bit.
 - Add interface heci_csr_clear_his() to clear H_IS bit. This function is called
   after H_IS checking (dev->host_hw_state & H_IS == H_IS).
 - In original heci_csr_disable_interrupts() function, it not only clears H_IE
   bit, sometimes it also clears H_IS bit. This patch separates the two parts.
 - Avoid calling write_heci_register() function to set H_CSR register directly,
   and instead using heci_set_csr_register() function

Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 6 insertions, 0 deletions

diff --git a/drivers/staging/heci/interrupt.c b/drivers/staging/heci/interrupt.c
index b7ce73be826..3a510ed3a3d 100644
--- a/drivers/staging/heci/interrupt.c
+++ b/drivers/staging/heci/interrupt.c
@@ -92,6 +92,9 @@ irqreturn_t heci_isr_interrupt(int irq, void *dev_id)
 	/* disable interrupts */
 	heci_csr_disable_interrupts(dev);
 
+	/* clear H_IS bit in H_CSR */
+	heci_csr_clear_his(dev);
+
 	/*
 	 * Our device interrupted, schedule work the heci_bh_handler
 	 * to handle the interrupt processing. This needs to be a
@@ -251,6 +254,9 @@ end:
 		/* acknowledge interrupt and disable interrupts */
 		heci_csr_disable_interrupts(dev);
 
+		/* clear H_IS bit in H_CSR */
+		heci_csr_clear_his(dev);
+
 		PREPARE_WORK(&dev->work, heci_bh_handler);
 		DBG("schedule work the heci_bh_handler.\n");
 		rets = schedule_work(&dev->work);