Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6: (1244 commits)
  pkt_sched: Rename PSCHED_US2NS and PSCHED_NS2US
  ipv4: Fix fib_trie rebalancing
  Bluetooth: Fix issue with uninitialized nsh.type in DTL-1 driver
  Bluetooth: Fix Kconfig issue with RFKILL integration
  PIM-SM: namespace changes
  ipv4: update ARPD help text
  net: use a deferred timer in rt_check_expire
  ieee802154: fix kconfig bool/tristate muckup
  bonding: initialization rework
  bonding: use is_zero_ether_addr
  bonding: network device names are case sensative
  bonding: elminate bad refcount code
  bonding: fix style issues
  bonding: fix destructor
  bonding: remove bonding read/write semaphore
  bonding: initialize before registration
  bonding: bond_create always called with default parameters
  x_tables: Convert printk to pr_err
  netfilter: conntrack: optional reliable conntrack event delivery
  list_nulls: add hlist_nulls_add_head and hlist_nulls_del
  ...

1 files changed, 0 insertions, 16322 deletions

diff --git a/drivers/net/bnx2x_init_values.h b/drivers/net/bnx2x_init_values.h
deleted file mode 100644
index 1f22c9ab66d..00000000000
--- a/drivers/net/bnx2x_init_values.h
+++ /dev/null
@@ -1,16322 +0,0 @@
-#ifndef __BNX2X_INIT_VALUES_H__
-#define __BNX2X_INIT_VALUES_H__
-
-/* bnx2x_init_values.h: Broadcom NX2 10G network driver.
- *
- * Copyright (c) 2007-2009 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, except as noted below.
- *
- * This file contains firmware data derived from proprietary unpublished
- * source code, Copyright (c) 2007-2009 Broadcom Corporation.
- *
- * Permission is hereby granted for the distribution of this firmware data
- * in hexadecimal or equivalent format, provided this copyright notice is
- * accompanying it.
- *
- *
- * This array contains the list of operations needed to initialize the chip.
- *
- * For each block in the chip there are three init stages:
- * common - HW used by both ports,
- * port1 and port2 - initialization for a specific Ethernet port.
- * When a port is opened or closed, the management CPU tells the driver
- * whether to init/disable common HW in addition to the port HW.
- * This way the first port going up will first initializes the common HW,
- * and the last port going down also resets the common HW
- *
- * For each init stage/block there is a list of actions needed in a format:
- * {operation, register, data}
- * where:
- * OP_WR - write a value to the chip.
- * OP_RD - read a register (usually a clear on read register).
- * OP_SW - string write, write a section of consecutive addresses to the chip.
- * OP_SI - copy a string using indirect writes.
- * OP_ZR - clear a range of memory.
- * OP_ZP - unzip and copy using DMAE.
- * OP_WB - string copy using DMAE.
- *
- * The #defines mark the stages.
- *
- */
-
-static const struct raw_op init_ops[] = {
-#define PRS_COMMON_START        0
-	{OP_WR, PRS_REG_INC_VALUE, 0xf},
-	{OP_WR, PRS_REG_EVENT_ID_1, 0x45},
-	{OP_WR, PRS_REG_EVENT_ID_2, 0x84},
-	{OP_WR, PRS_REG_EVENT_ID_3, 0x6},
-	{OP_WR, PRS_REG_NO_MATCH_EVENT_ID, 0x4},
-	{OP_WR, PRS_REG_CM_HDR_TYPE_0, 0x0},
-	{OP_WR, PRS_REG_CM_HDR_TYPE_1, 0x12170000},
-	{OP_WR, PRS_REG_CM_HDR_TYPE_2, 0x22170000},
-	{OP_WR, PRS_REG_CM_HDR_TYPE_3, 0x32170000},
-	{OP_ZR, PRS_REG_CM_HDR_TYPE_4, 0x5},
-	{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_1, 0x12150000},
-	{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_2, 0x22150000},
-	{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_3, 0x32150000},
-	{OP_ZR, PRS_REG_CM_HDR_LOOPBACK_TYPE_4, 0x4},
-	{OP_WR, PRS_REG_CM_NO_MATCH_HDR, 0x2100000},
-	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0, 0x100000},
-	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1, 0x10100000},
-	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2, 0x20100000},
-	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3, 0x30100000},
-	{OP_ZR_E1, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x4},
-	{OP_WR_E1H, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x40100000},
-	{OP_ZR_E1H, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5, 0x3},
-	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0, 0x100000},
-	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1, 0x12140000},
-	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2, 0x22140000},
-	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3, 0x32140000},
-	{OP_ZR_E1, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x4},
-	{OP_WR_E1H, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x42140000},
-	{OP_ZR_E1H, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5, 0x3},
-	{OP_RD, PRS_REG_NUM_OF_PACKETS, 0x0},
-	{OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0},
-	{OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0},
-	{OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0},
-	{OP_WR_E1H, PRS_REG_FCOE_TYPE, 0x8906},
-	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff},
-	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff},
-	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff},
-	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_3, 0xff},
-	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_4, 0xff},
-	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_5, 0xff},
-	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_6, 0xff},
-	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_7, 0xff},
-	{OP_WR, PRS_REG_PURE_REGIONS, 0x3e},
-	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_0, 0x0},
-	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_1, 0x3f},
-	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_2, 0x3f},
-	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_3, 0x3f},
-	{OP_WR_E1, PRS_REG_PACKET_REGIONS_TYPE_4, 0x0},
-	{OP_WR_E1H, PRS_REG_PACKET_REGIONS_TYPE_4, 0x3f},
-	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f},
-	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f},
-	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f},
-#define PRS_COMMON_END          52
-#define SRCH_COMMON_START       52
-	{OP_WR_E1H, SRC_REG_E1HMF_ENABLE, 0x1},
-#define SRCH_COMMON_END         53
-#define TSDM_COMMON_START       53
-	{OP_WR_E1, TSDM_REG_CFC_RSP_START_ADDR, 0x411},
-	{OP_WR_E1H, TSDM_REG_CFC_RSP_START_ADDR, 0x211},
-	{OP_WR_E1, TSDM_REG_CMP_COUNTER_START_ADDR, 0x400},
-	{OP_WR_E1H, TSDM_REG_CMP_COUNTER_START_ADDR, 0x200},
-	{OP_WR_E1, TSDM_REG_Q_COUNTER_START_ADDR, 0x404},
-	{OP_WR_E1H, TSDM_REG_Q_COUNTER_START_ADDR, 0x204},
-	{OP_WR_E1, TSDM_REG_PCK_END_MSG_START_ADDR, 0x419},
-	{OP_WR_E1H, TSDM_REG_PCK_END_MSG_START_ADDR, 0x219},
-	{OP_WR, TSDM_REG_CMP_COUNTER_MAX0, 0xffff},
-	{OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff},
-	{OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff},
-	{OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff},
-	{OP_ZR_E1, TSDM_REG_AGG_INT_EVENT_0, 0x2},
-	{OP_WR_E1H, TSDM_REG_AGG_INT_EVENT_0, 0x20},
-	{OP_WR_E1H, TSDM_REG_AGG_INT_EVENT_1, 0x0},
-	{OP_WR, TSDM_REG_AGG_INT_EVENT_2, 0x34},
-	{OP_WR, TSDM_REG_AGG_INT_EVENT_3, 0x35},
-	{OP_ZR_E1, TSDM_REG_AGG_INT_EVENT_4, 0x7c},
-	{OP_ZR_E1H, TSDM_REG_AGG_INT_EVENT_4, 0x1c},
-	{OP_WR_E1H, TSDM_REG_AGG_INT_T_0, 0x1},
-	{OP_ZR_E1H, TSDM_REG_AGG_INT_T_1, 0x5f},
-	{OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff},
-	{OP_WR, TSDM_REG_ENABLE_IN2, 0x3f},
-	{OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff},
-	{OP_WR, TSDM_REG_ENABLE_OUT2, 0xf},
-	{OP_RD, TSDM_REG_NUM_OF_Q0_CMD, 0x0},
-	{OP_RD, TSDM_REG_NUM_OF_Q1_CMD, 0x0},
-	{OP_RD, TSDM_REG_NUM_OF_Q3_CMD, 0x0},
-	{OP_RD, TSDM_REG_NUM_OF_Q4_CMD, 0x0},
-	{OP_RD, TSDM_REG_NUM_OF_Q5_CMD, 0x0},
-	{OP_RD, TSDM_REG_NUM_OF_Q6_CMD, 0x0},
-	{OP_RD, TSDM_REG_NUM_OF_Q7_CMD, 0x0},
-	{OP_RD, TSDM_REG_NUM_OF_Q8_CMD, 0x0},
-	{OP_RD, TSDM_REG_NUM_OF_Q9_CMD, 0x0},
-	{OP_RD, TSDM_REG_NUM_OF_Q10_CMD, 0x0},
-	{OP_RD, TSDM_REG_NUM_OF_Q11_CMD, 0x0},
-	{OP_RD, TSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
-	{OP_RD, TSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
-	{OP_RD, TSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
-	{OP_WR_E1, TSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
-	{OP_WR_ASIC, TSDM_REG_TIMER_TICK, 0x3e8},
-	{OP_WR_EMUL, TSDM_REG_TIMER_TICK, 0x1},
-	{OP_WR_FPGA, TSDM_REG_TIMER_TICK, 0xa},
-#define TSDM_COMMON_END         96
-#define TCM_COMMON_START        96
-	{OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20},
-	{OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32},
-	{OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020},
-	{OP_WR, TCM_REG_TQM_TCM_HDR_S, 0x2150020},
-	{OP_WR, TCM_REG_TM_TCM_HDR, 0x30},
-	{OP_WR, TCM_REG_ERR_TCM_HDR, 0x8100000},
-	{OP_WR, TCM_REG_ERR_EVNT_ID, 0x33},
-	{OP_WR, TCM_REG_EXPR_EVNT_ID, 0x30},
-	{OP_WR, TCM_REG_STOP_EVNT_ID, 0x31},
-	{OP_WR, TCM_REG_STORM_WEIGHT, 0x2},
-	{OP_WR, TCM_REG_PRS_WEIGHT, 0x5},
-	{OP_WR, TCM_REG_PBF_WEIGHT, 0x6},
-	{OP_WR, TCM_REG_USEM_WEIGHT, 0x2},
-	{OP_WR, TCM_REG_CSEM_WEIGHT, 0x2},
-	{OP_WR, TCM_REG_CP_WEIGHT, 0x0},
-	{OP_WR, TCM_REG_TSDM_WEIGHT, 0x5},
-	{OP_WR, TCM_REG_TQM_P_WEIGHT, 0x2},
-	{OP_WR, TCM_REG_TQM_S_WEIGHT, 0x2},
-	{OP_WR, TCM_REG_TM_WEIGHT, 0x2},
-	{OP_WR, TCM_REG_TCM_TQM_USE_Q, 0x1},
-	{OP_WR, TCM_REG_GR_ARB_TYPE, 0x1},
-	{OP_WR, TCM_REG_GR_LD0_PR, 0x1},
-	{OP_WR, TCM_REG_GR_LD1_PR, 0x2},
-	{OP_WR, TCM_REG_CFC_INIT_CRD, 0x1},
-	{OP_WR, TCM_REG_FIC0_INIT_CRD, 0x40},
-	{OP_WR, TCM_REG_FIC1_INIT_CRD, 0x40},
-	{OP_WR, TCM_REG_TQM_INIT_CRD, 0x20},
-	{OP_WR, TCM_REG_XX_INIT_CRD, 0x13},
-	{OP_WR, TCM_REG_XX_MSG_NUM, 0x20},
-	{OP_ZR, TCM_REG_XX_TABLE, 0xa},
-	{OP_SW, TCM_REG_XX_DESCR_TABLE, 0x200000},
-	{OP_WR, TCM_REG_N_SM_CTX_LD_0, 0x7},
-	{OP_WR, TCM_REG_N_SM_CTX_LD_1, 0x7},
-	{OP_WR, TCM_REG_N_SM_CTX_LD_2, 0x8},
-	{OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8},
-	{OP_ZR_E1, TCM_REG_N_SM_CTX_LD_4, 0x4},
-	{OP_WR_E1H, TCM_REG_N_SM_CTX_LD_4, 0x1},
-	{OP_ZR_E1H, TCM_REG_N_SM_CTX_LD_5, 0x3},
-	{OP_WR, TCM_REG_TCM_REG0_SZ, 0x6},
-	{OP_WR_E1, TCM_REG_PHYS_QNUM0_0, 0xd},
-	{OP_WR_E1, TCM_REG_PHYS_QNUM0_1, 0x2d},
-	{OP_WR_E1, TCM_REG_PHYS_QNUM1_0, 0x7},
-	{OP_WR_E1, TCM_REG_PHYS_QNUM1_1, 0x27},
-	{OP_WR_E1, TCM_REG_PHYS_QNUM2_0, 0x7},
-	{OP_WR_E1, TCM_REG_PHYS_QNUM2_1, 0x27},
-	{OP_WR_E1, TCM_REG_PHYS_QNUM3_0, 0x7},
-	{OP_WR_E1, TCM_REG_PHYS_QNUM3_1, 0x27},
-	{OP_WR, TCM_REG_TCM_STORM0_IFEN, 0x1},
-	{OP_WR, TCM_REG_TCM_STORM1_IFEN, 0x1},
-	{OP_WR, TCM_REG_TCM_TQM_IFEN, 0x1},
-	{OP_WR, TCM_REG_STORM_TCM_IFEN, 0x1},
-	{OP_WR, TCM_REG_TQM_TCM_IFEN, 0x1},
-	{OP_WR, TCM_REG_TSDM_IFEN, 0x1},
-	{OP_WR, TCM_REG_TM_TCM_IFEN, 0x1},
-	{OP_WR, TCM_REG_PRS_IFEN, 0x1},
-	{OP_WR, TCM_REG_PBF_IFEN, 0x1},
-	{OP_WR, TCM_REG_USEM_IFEN, 0x1},
-	{OP_WR, TCM_REG_CSEM_IFEN, 0x1},
-	{OP_WR, TCM_REG_CDU_AG_WR_IFEN, 0x1},
-	{OP_WR, TCM_REG_CDU_AG_RD_IFEN, 0x1},
-	{OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1},
-	{OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1},
-	{OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1},
-#define TCM_COMMON_END          159
-#define TCM_FUNC0_START         159
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0xd},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x7},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x7},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x7},
-#define TCM_FUNC0_END           163
-#define TCM_FUNC1_START         163
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x2d},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x27},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x27},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x27},
-#define TCM_FUNC1_END           167
-#define TCM_FUNC2_START         167
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x1d},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x17},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x17},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x17},
-#define TCM_FUNC2_END           171
-#define TCM_FUNC3_START         171
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x3d},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x37},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x37},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x37},
-#define TCM_FUNC3_END           175
-#define TCM_FUNC4_START         175
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x4d},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x47},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x47},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x47},
-#define TCM_FUNC4_END           179
-#define TCM_FUNC5_START         179
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x6d},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x67},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x67},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x67},
-#define TCM_FUNC5_END           183
-#define TCM_FUNC6_START         183
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x5d},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x57},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x57},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x57},
-#define TCM_FUNC6_END           187
-#define TCM_FUNC7_START         187
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x7d},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x77},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x77},
-	{OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x77},
-#define TCM_FUNC7_END           191
-#define BRB1_COMMON_START       191
-	{OP_SW, BRB1_REG_LL_RAM, 0x2000020},
-	{OP_WR, BRB1_REG_SOFT_RESET, 0x1},
-	{OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0},
-	{OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220},
-	{OP_WR, BRB1_REG_SOFT_RESET, 0x0},
-#define BRB1_COMMON_END         196
-#define BRB1_PORT0_START        196
-	{OP_WR_E1, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0xb8},
-	{OP_WR_E1, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 0x114},
-	{OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0},
-	{OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0},
-#define BRB1_PORT0_END          200
-#define BRB1_PORT1_START        200
-	{OP_WR_E1, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0xb8},
-	{OP_WR_E1, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 0x114},
-	{OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0},
-	{OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0},
-#define BRB1_PORT1_END          204
-#define TSEM_COMMON_START       204
-	{OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0},
-	{OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0},
-	{OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0},
-	{OP_RD, TSEM_REG_MSG_NUM_FOC1, 0x0},
-	{OP_RD, TSEM_REG_MSG_NUM_FOC2, 0x0},
-	{OP_RD, TSEM_REG_MSG_NUM_FOC3, 0x0},
-	{OP_WR, TSEM_REG_ARB_ELEMENT0, 0x1},
-	{OP_WR, TSEM_REG_ARB_ELEMENT1, 0x2},
-	{OP_WR, TSEM_REG_ARB_ELEMENT2, 0x3},
-	{OP_WR, TSEM_REG_ARB_ELEMENT3, 0x0},
-	{OP_WR, TSEM_REG_ARB_ELEMENT4, 0x4},
-	{OP_WR, TSEM_REG_ARB_CYCLE_SIZE, 0x1},
-	{OP_WR, TSEM_REG_TS_0_AS, 0x0},
-	{OP_WR, TSEM_REG_TS_1_AS, 0x1},
-	{OP_WR, TSEM_REG_TS_2_AS, 0x4},
-	{OP_WR, TSEM_REG_TS_3_AS, 0x0},
-	{OP_WR, TSEM_REG_TS_4_AS, 0x1},
-	{OP_WR, TSEM_REG_TS_5_AS, 0x3},
-	{OP_WR, TSEM_REG_TS_6_AS, 0x0},
-	{OP_WR, TSEM_REG_TS_7_AS, 0x1},
-	{OP_WR, TSEM_REG_TS_8_AS, 0x4},
-	{OP_WR, TSEM_REG_TS_9_AS, 0x0},
-	{OP_WR, TSEM_REG_TS_10_AS, 0x1},
-	{OP_WR, TSEM_REG_TS_11_AS, 0x3},
-	{OP_WR, TSEM_REG_TS_12_AS, 0x0},
-	{OP_WR, TSEM_REG_TS_13_AS, 0x1},
-	{OP_WR, TSEM_REG_TS_14_AS, 0x4},
-	{OP_WR, TSEM_REG_TS_15_AS, 0x0},
-	{OP_WR, TSEM_REG_TS_16_AS, 0x4},
-	{OP_WR, TSEM_REG_TS_17_AS, 0x3},
-	{OP_ZR, TSEM_REG_TS_18_AS, 0x2},
-	{OP_WR, TSEM_REG_ENABLE_IN, 0x3fff},
-	{OP_WR, TSEM_REG_ENABLE_OUT, 0x3ff},
-	{OP_WR, TSEM_REG_FIC0_DISABLE, 0x0},
-	{OP_WR, TSEM_REG_FIC1_DISABLE, 0x0},
-	{OP_WR, TSEM_REG_PAS_DISABLE, 0x0},
-	{OP_WR, TSEM_REG_THREADS_LIST, 0xff},
-	{OP_ZR, TSEM_REG_PASSIVE_BUFFER, 0x400},
-	{OP_WR, TSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
-	{OP_WR, TSEM_REG_FAST_MEMORY + 0x18000, 0x34},
-	{OP_WR, TSEM_REG_FAST_MEMORY + 0x18040, 0x18},
-	{OP_WR, TSEM_REG_FAST_MEMORY + 0x18080, 0xc},
-	{OP_WR, TSEM_REG_FAST_MEMORY + 0x180c0, 0x20},
-	{OP_WR_ASIC, TSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
-	{OP_WR_EMUL, TSEM_REG_FAST_MEMORY + 0x18300, 0x138},
-	{OP_WR_FPGA, TSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
-	{OP_WR, TSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2000, 0xb2},
-	{OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x11480, 0x1},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x23c8, 0xc1},
-	{OP_WR_EMUL_E1H, TSEM_REG_FAST_MEMORY + 0x11480, 0x0},
-	{OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x23c8 + 0x304, 0x10223},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x1000, 0x2b3},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
-	{OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x1000 + 0xacc, 0x10223},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1000, 0x2},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xa020, 0xc8},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1c18, 0x4},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xa000, 0x2},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1c10, 0x2},
-	{OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x1ad0, 0x0},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x800, 0x2},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x1ad8, 0x4},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x808, 0x2},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3678, 0x6},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x810, 0x4},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3670, 0x2},
-	{OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x40224},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2},
-	{OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x4cb0, 0x80228},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5008, 0x4},
-	{OP_ZP_E1, TSEM_REG_INT_TABLE, 0x930000},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5018, 0x4},
-	{OP_WR_64_E1, TSEM_REG_INT_TABLE + 0x360, 0x140230},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5028, 0x4},
-	{OP_ZP_E1, TSEM_REG_PRAM, 0x324f0000},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5038, 0x4},
-	{OP_ZP_E1, TSEM_REG_PRAM + 0x8000, 0x33250c94},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5048, 0x4},
-	{OP_ZP_E1, TSEM_REG_PRAM + 0x10000, 0xe4d195e},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5058, 0x4},
-	{OP_WR_64_E1, TSEM_REG_PRAM + 0x11e00, 0x5c400232},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5068, 0x4},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5078, 0x2},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2},
-	{OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x62c0, 0x200224},
-	{OP_ZP_E1H, TSEM_REG_INT_TABLE, 0x9b0000},
-	{OP_WR_64_E1H, TSEM_REG_INT_TABLE + 0x398, 0xd0244},
-	{OP_ZP_E1H, TSEM_REG_PRAM, 0x325e0000},
-	{OP_ZP_E1H, TSEM_REG_PRAM + 0x8000, 0x35960c98},
-	{OP_ZP_E1H, TSEM_REG_PRAM + 0x10000, 0x1aea19fe},
-	{OP_WR_64_E1H, TSEM_REG_PRAM + 0x143d0, 0x57860246},
-#define TSEM_COMMON_END         297
-#define TSEM_PORT0_START        297
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x22c8, 0x20},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x2000, 0x16c},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x4000, 0x16c},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb000, 0x28},
-	{OP_WR_E1, TSEM_REG_FAST_MEMORY + 0x4b60, 0x0},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb140, 0xc},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1400, 0xa},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x32c0, 0x12},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1450, 0x6},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3350, 0x64},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1500, 0x2},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x8108, 0x2},
-	{OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1500 + 0x8, 0x50234},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1500 + 0x1c, 0x7},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1570, 0x12},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x9c0, 0x4c},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x800, 0x2},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x820, 0xe},
-	{OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x20239},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2908, 0x2},
-#define TSEM_PORT0_END          317
-#define TSEM_PORT1_START        317
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2348, 0x20},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x25b0, 0x16c},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x45b0, 0x16c},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb0a0, 0x28},
-	{OP_WR_E1, TSEM_REG_FAST_MEMORY + 0x4b64, 0x0},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb170, 0xc},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1428, 0xa},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3308, 0x12},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1468, 0x6},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x34e0, 0x64},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1538, 0x2},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x8110, 0x2},
-	{OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1538 + 0x8, 0x5023b},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1538 + 0x1c, 0x7},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x15b8, 0x12},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0xaf0, 0x4c},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x808, 0x2},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x858, 0xe},
-	{OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb8, 0x20240},
-	{OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2910, 0x2},
-#define TSEM_PORT1_END          337
-#define TSEM_FUNC0_START        337
-	{OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b60, 0x0},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3000, 0x2},
-	{OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3000 + 0x8, 0x50248},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3000 + 0x1c, 0x7},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31c0, 0x8},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5080, 0x12},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2},
-#define TSEM_FUNC0_END          345
-#define TSEM_FUNC1_START        345
-	{OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b64, 0x0},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3038, 0x2},
-	{OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3038 + 0x8, 0x5024d},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3038 + 0x1c, 0x7},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31e0, 0x8},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5010, 0x2},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x50c8, 0x12},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2},
-#define TSEM_FUNC1_END          353
-#define TSEM_FUNC2_START        353
-	{OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b68, 0x0},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3070, 0x2},
-	{OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3070 + 0x8, 0x50252},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3070 + 0x1c, 0x7},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3200, 0x8},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5020, 0x2},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5110, 0x12},
-	{OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4010, 0x20257},
-#define TSEM_FUNC2_END          361
-#define TSEM_FUNC3_START        361
-	{OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b6c, 0x0},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30a8, 0x2},
-	{OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x30a8 + 0x8, 0x50259},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30a8 + 0x1c, 0x7},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3220, 0x8},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5030, 0x2},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5158, 0x12},
-	{OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4018, 0x2025e},
-#define TSEM_FUNC3_END          369
-#define TSEM_FUNC4_START        369
-	{OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b70, 0x0},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30e0, 0x2},
-	{OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x30e0 + 0x8, 0x50260},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30e0 + 0x1c, 0x7},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3240, 0x8},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5040, 0x2},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51a0, 0x12},
-	{OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4020, 0x20265},
-#define TSEM_FUNC4_END          377
-#define TSEM_FUNC5_START        377
-	{OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b74, 0x0},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3118, 0x2},
-	{OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3118 + 0x8, 0x50267},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3118 + 0x1c, 0x7},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3260, 0x8},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5050, 0x2},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51e8, 0x12},
-	{OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4028, 0x2026c},
-#define TSEM_FUNC5_END          385
-#define TSEM_FUNC6_START        385
-	{OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b78, 0x0},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3150, 0x2},
-	{OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3150 + 0x8, 0x5026e},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3150 + 0x1c, 0x7},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3280, 0x8},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5060, 0x2},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5230, 0x12},
-	{OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4030, 0x20273},
-#define TSEM_FUNC6_END          393
-#define TSEM_FUNC7_START        393
-	{OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b7c, 0x0},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3188, 0x2},
-	{OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x3188 + 0x8, 0x50275},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3188 + 0x1c, 0x7},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x32a0, 0x8},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5070, 0x2},
-	{OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5278, 0x12},
-	{OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4038, 0x2027a},
-#define TSEM_FUNC7_END          401
-#define MISC_COMMON_START       401
-	{OP_WR_E1, MISC_REG_GRC_TIMEOUT_EN, 0x1},
-	{OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911},
-	{OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0},
-	{OP_WR, MISC_REG_PLL_STORM_CTRL_3, 0x9c0424},
-	{OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0},
-	{OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209},
-	{OP_WR_E1, MISC_REG_SPIO, 0xff000000},
-#define MISC_COMMON_END         408
-#define MISC_FUNC0_START        408
-	{OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
-#define MISC_FUNC0_END          409
-#define MISC_FUNC1_START        409
-	{OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
-#define MISC_FUNC1_END          410
-#define MISC_FUNC2_START        410
-	{OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
-#define MISC_FUNC2_END          411
-#define MISC_FUNC3_START        411
-	{OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
-#define MISC_FUNC3_END          412
-#define MISC_FUNC4_START        412
-	{OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
-#define MISC_FUNC4_END          413
-#define MISC_FUNC5_START        413
-	{OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
-#define MISC_FUNC5_END          414
-#define MISC_FUNC6_START        414
-	{OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
-#define MISC_FUNC6_END          415
-#define MISC_FUNC7_START        415
-	{OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
-#define MISC_FUNC7_END          416
-#define NIG_COMMON_START        416
-	{OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1},
-	{OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1},
-	{OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1},
-	{OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1},
-	{OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1},
-#define NIG_COMMON_END          421
-#define NIG_PORT0_START         421
-	{OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000},
-	{OP_WR, NIG_REG_LLH0_EVENT_ID, 0x28},
-	{OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0},
-	{OP_WR, NIG_REG_LLH0_XCM_MASK, 0x4},
-	{OP_WR, NIG_REG_LLH0_BRB1_NOT_MCP, 0x1},
-	{OP_WR, NIG_REG_STATUS_INTERRUPT_PORT0, 0x0},
-	{OP_WR_E1H, NIG_REG_LLH0_CLS_TYPE, 0x1},
-	{OP_WR, NIG_REG_LLH0_XCM_INIT_CREDIT, 0x30},
-	{OP_WR, NIG_REG_BRB0_PAUSE_IN_EN, 0x1},
-	{OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1},
-	{OP_WR, NIG_REG_BRB0_OUT_EN, 0x1},
-	{OP_WR, NIG_REG_XCM0_OUT_EN, 0x1},
-#define NIG_PORT0_END           433
-#define NIG_PORT1_START         433
-	{OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000},
-	{OP_WR, NIG_REG_LLH1_EVENT_ID, 0x28},
-	{OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0},
-	{OP_WR, NIG_REG_LLH1_XCM_MASK, 0x4},
-	{OP_WR, NIG_REG_LLH1_BRB1_NOT_MCP, 0x1},
-	{OP_WR, NIG_REG_STATUS_INTERRUPT_PORT1, 0x0},
-	{OP_WR_E1H, NIG_REG_LLH1_CLS_TYPE, 0x1},
-	{OP_WR, NIG_REG_LLH1_XCM_INIT_CREDIT, 0x30},
-	{OP_WR, NIG_REG_BRB1_PAUSE_IN_EN, 0x1},
-	{OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1},
-	{OP_WR, NIG_REG_BRB1_OUT_EN, 0x1},
-	{OP_WR, NIG_REG_XCM1_OUT_EN, 0x1},
-#define NIG_PORT1_END           445
-#define UPB_COMMON_START        445
-	{OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20},
-#define UPB_COMMON_END          446
-#define CSDM_COMMON_START       446
-	{OP_WR_E1, CSDM_REG_CFC_RSP_START_ADDR, 0xa11},
-	{OP_WR_E1H, CSDM_REG_CFC_RSP_START_ADDR, 0x211},
-	{OP_WR_E1, CSDM_REG_CMP_COUNTER_START_ADDR, 0xa00},
-	{OP_WR_E1H, CSDM_REG_CMP_COUNTER_START_ADDR, 0x200},
-	{OP_WR_E1, CSDM_REG_Q_COUNTER_START_ADDR, 0xa04},
-	{OP_WR_E1H, CSDM_REG_Q_COUNTER_START_ADDR, 0x204},
-	{OP_WR, CSDM_REG_CMP_COUNTER_MAX0, 0xffff},
-	{OP_WR, CSDM_REG_CMP_COUNTER_MAX1, 0xffff},
-	{OP_WR, CSDM_REG_CMP_COUNTER_MAX2, 0xffff},
-	{OP_WR, CSDM_REG_CMP_COUNTER_MAX3, 0xffff},
-	{OP_WR, CSDM_REG_AGG_INT_EVENT_0, 0xc6},
-	{OP_WR, CSDM_REG_AGG_INT_EVENT_1, 0x0},
-	{OP_WR, CSDM_REG_AGG_INT_EVENT_2, 0x34},
-	{OP_WR, CSDM_REG_AGG_INT_EVENT_3, 0x35},
-	{OP_ZR, CSDM_REG_AGG_INT_EVENT_4, 0x1c},
-	{OP_WR, CSDM_REG_AGG_INT_T_0, 0x1},
-	{OP_ZR, CSDM_REG_AGG_INT_T_1, 0x5f},
-	{OP_WR, CSDM_REG_ENABLE_IN1, 0x7ffffff},
-	{OP_WR, CSDM_REG_ENABLE_IN2, 0x3f},
-	{OP_WR, CSDM_REG_ENABLE_OUT1, 0x7ffffff},
-	{OP_WR, CSDM_REG_ENABLE_OUT2, 0xf},
-	{OP_RD, CSDM_REG_NUM_OF_Q0_CMD, 0x0},
-	{OP_RD, CSDM_REG_NUM_OF_Q1_CMD, 0x0},
-	{OP_RD, CSDM_REG_NUM_OF_Q3_CMD, 0x0},
-	{OP_RD, CSDM_REG_NUM_OF_Q4_CMD, 0x0},
-	{OP_RD, CSDM_REG_NUM_OF_Q5_CMD, 0x0},
-	{OP_RD, CSDM_REG_NUM_OF_Q6_CMD, 0x0},
-	{OP_RD, CSDM_REG_NUM_OF_Q7_CMD, 0x0},
-	{OP_RD, CSDM_REG_NUM_OF_Q8_CMD, 0x0},
-	{OP_RD, CSDM_REG_NUM_OF_Q9_CMD, 0x0},
-	{OP_RD, CSDM_REG_NUM_OF_Q10_CMD, 0x0},
-	{OP_RD, CSDM_REG_NUM_OF_Q11_CMD, 0x0},
-	{OP_RD, CSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
-	{OP_RD, CSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
-	{OP_RD, CSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
-	{OP_WR_E1, CSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
-	{OP_WR_ASIC, CSDM_REG_TIMER_TICK, 0x3e8},
-	{OP_WR_EMUL, CSDM_REG_TIMER_TICK, 0x1},
-	{OP_WR_FPGA, CSDM_REG_TIMER_TICK, 0xa},
-#define CSDM_COMMON_END         485
-#define USDM_COMMON_START       485
-	{OP_WR_E1, USDM_REG_CFC_RSP_START_ADDR, 0xa11},
-	{OP_WR_E1H, USDM_REG_CFC_RSP_START_ADDR, 0x411},
-	{OP_WR_E1, USDM_REG_CMP_COUNTER_START_ADDR, 0xa00},
-	{OP_WR_E1H, USDM_REG_CMP_COUNTER_START_ADDR, 0x400},
-	{OP_WR_E1, USDM_REG_Q_COUNTER_START_ADDR, 0xa04},
-	{OP_WR_E1H, USDM_REG_Q_COUNTER_START_ADDR, 0x404},
-	{OP_WR_E1, USDM_REG_PCK_END_MSG_START_ADDR, 0xa21},
-	{OP_WR_E1H, USDM_REG_PCK_END_MSG_START_ADDR, 0x421},
-	{OP_WR, USDM_REG_CMP_COUNTER_MAX0, 0xffff},
-	{OP_WR, USDM_REG_CMP_COUNTER_MAX1, 0xffff},
-	{OP_WR, USDM_REG_CMP_COUNTER_MAX2, 0xffff},
-	{OP_WR, USDM_REG_CMP_COUNTER_MAX3, 0xffff},
-	{OP_WR, USDM_REG_AGG_INT_EVENT_0, 0x46},
-	{OP_WR, USDM_REG_AGG_INT_EVENT_1, 0x5},
-	{OP_WR, USDM_REG_AGG_INT_EVENT_2, 0x34},
-	{OP_WR, USDM_REG_AGG_INT_EVENT_3, 0x35},
-	{OP_ZR_E1, USDM_REG_AGG_INT_EVENT_4, 0x5c},
-	{OP_WR_E1H, USDM_REG_AGG_INT_EVENT_4, 0x7},
-	{OP_ZR_E1H, USDM_REG_AGG_INT_EVENT_5, 0x5b},
-	{OP_WR, USDM_REG_AGG_INT_MODE_0, 0x1},
-	{OP_ZR_E1, USDM_REG_AGG_INT_MODE_1, 0x1f},
-	{OP_ZR_E1H, USDM_REG_AGG_INT_MODE_1, 0x3},
-	{OP_WR_E1H, USDM_REG_AGG_INT_MODE_4, 0x1},
-	{OP_ZR_E1H, USDM_REG_AGG_INT_MODE_5, 0x1b},
-	{OP_WR, USDM_REG_ENABLE_IN1, 0x7ffffff},
-	{OP_WR, USDM_REG_ENABLE_IN2, 0x3f},
-	{OP_WR, USDM_REG_ENABLE_OUT1, 0x7ffffff},
-	{OP_WR, USDM_REG_ENABLE_OUT2, 0xf},
-	{OP_RD, USDM_REG_NUM_OF_Q0_CMD, 0x0},
-	{OP_RD, USDM_REG_NUM_OF_Q1_CMD, 0x0},
-	{OP_RD, USDM_REG_NUM_OF_Q2_CMD, 0x0},
-	{OP_RD, USDM_REG_NUM_OF_Q3_CMD, 0x0},
-	{OP_RD, USDM_REG_NUM_OF_Q4_CMD, 0x0},
-	{OP_RD, USDM_REG_NUM_OF_Q5_CMD, 0x0},
-	{OP_RD, USDM_REG_NUM_OF_Q6_CMD, 0x0},
-	{OP_RD, USDM_REG_NUM_OF_Q7_CMD, 0x0},
-	{OP_RD, USDM_REG_NUM_OF_Q8_CMD, 0x0},
-	{OP_RD, USDM_REG_NUM_OF_Q9_CMD, 0x0},
-	{OP_RD, USDM_REG_NUM_OF_Q10_CMD, 0x0},
-	{OP_RD, USDM_REG_NUM_OF_Q11_CMD, 0x0},
-	{OP_RD, USDM_REG_NUM_OF_PKT_END_MSG, 0x0},
-	{OP_RD, USDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
-	{OP_RD, USDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
-	{OP_WR_E1, USDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
-	{OP_WR_ASIC, USDM_REG_TIMER_TICK, 0x3e8},
-	{OP_WR_EMUL, USDM_REG_TIMER_TICK, 0x1},
-	{OP_WR_FPGA, USDM_REG_TIMER_TICK, 0xa},
-#define USDM_COMMON_END         532
-#define CCM_COMMON_START        532
-	{OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32},
-	{OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020},
-	{OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020},
-	{OP_WR, CCM_REG_ERR_CCM_HDR, 0x8100000},
-	{OP_WR, CCM_REG_ERR_EVNT_ID, 0x33},
-	{OP_WR, CCM_REG_STORM_WEIGHT, 0x2},
-	{OP_WR, CCM_REG_TSEM_WEIGHT, 0x0},
-	{OP_WR, CCM_REG_XSEM_WEIGHT, 0x5},
-	{OP_WR, CCM_REG_USEM_WEIGHT, 0x5},
-	{OP_ZR, CCM_REG_PBF_WEIGHT, 0x2},
-	{OP_WR, CCM_REG_CSDM_WEIGHT, 0x2},
-	{OP_WR, CCM_REG_CQM_P_WEIGHT, 0x3},
-	{OP_WR, CCM_REG_CQM_S_WEIGHT, 0x2},
-	{OP_WR, CCM_REG_CCM_CQM_USE_Q, 0x1},
-	{OP_WR, CCM_REG_CNT_AUX1_Q, 0x2},
-	{OP_WR, CCM_REG_CNT_AUX2_Q, 0x2},
-	{OP_WR, CCM_REG_INV_DONE_Q, 0x1},
-	{OP_WR, CCM_REG_GR_ARB_TYPE, 0x1},
-	{OP_WR, CCM_REG_GR_LD0_PR, 0x1},
-	{OP_WR, CCM_REG_GR_LD1_PR, 0x2},
-	{OP_WR, CCM_REG_CFC_INIT_CRD, 0x1},
-	{OP_WR, CCM_REG_CQM_INIT_CRD, 0x20},
-	{OP_WR, CCM_REG_FIC0_INIT_CRD, 0x40},
-	{OP_WR, CCM_REG_FIC1_INIT_CRD, 0x40},
-	{OP_WR, CCM_REG_XX_INIT_CRD, 0x3},
-	{OP_WR, CCM_REG_XX_MSG_NUM, 0x18},
-	{OP_ZR, CCM_REG_XX_TABLE, 0x12},
-	{OP_SW_E1, CCM_REG_XX_DESCR_TABLE, 0x240242},
-	{OP_SW_E1H, CCM_REG_XX_DESCR_TABLE, 0x24027c},
-	{OP_WR, CCM_REG_N_SM_CTX_LD_0, 0x1},
-	{OP_WR, CCM_REG_N_SM_CTX_LD_1, 0x2},
-	{OP_WR, CCM_REG_N_SM_CTX_LD_2, 0x8},
-	{OP_WR, CCM_REG_N_SM_CTX_LD_3, 0x8},
-	{OP_ZR, CCM_REG_N_SM_CTX_LD_4, 0x4},
-	{OP_WR, CCM_REG_CCM_REG0_SZ, 0x4},
-	{OP_WR_E1, CCM_REG_QOS_PHYS_QNUM0_0, 0x9},
-	{OP_WR_E1, CCM_REG_QOS_PHYS_QNUM0_1, 0x29},
-	{OP_WR_E1, CCM_REG_QOS_PHYS_QNUM1_0, 0xa},
-	{OP_WR_E1, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a},
-	{OP_WR_E1, CCM_REG_QOS_PHYS_QNUM2_0, 0x7},
-	{OP_WR_E1, CCM_REG_QOS_PHYS_QNUM2_1, 0x27},
-	{OP_WR_E1, CCM_REG_QOS_PHYS_QNUM3_0, 0x7},
-	{OP_WR_E1, CCM_REG_QOS_PHYS_QNUM3_1, 0x27},
-	{OP_WR_E1, CCM_REG_PHYS_QNUM1_0, 0xc},
-	{OP_WR_E1, CCM_REG_PHYS_QNUM1_1, 0x2c},
-	{OP_WR_E1, CCM_REG_PHYS_QNUM2_0, 0xc},
-	{OP_WR_E1, CCM_REG_PHYS_QNUM2_1, 0x2c},
-	{OP_WR_E1, CCM_REG_PHYS_QNUM3_0, 0xc},
-	{OP_WR_E1, CCM_REG_PHYS_QNUM3_1, 0x2c},
-	{OP_WR, CCM_REG_CCM_STORM0_IFEN, 0x1},
-	{OP_WR, CCM_REG_CCM_STORM1_IFEN, 0x1},
-	{OP_WR, CCM_REG_CCM_CQM_IFEN, 0x1},
-	{OP_WR, CCM_REG_STORM_CCM_IFEN, 0x1},
-	{OP_WR, CCM_REG_CQM_CCM_IFEN, 0x1},
-	{OP_WR, CCM_REG_CSDM_IFEN, 0x1},
-	{OP_WR, CCM_REG_TSEM_IFEN, 0x1},
-	{OP_WR, CCM_REG_XSEM_IFEN, 0x1},
-	{OP_WR, CCM_REG_USEM_IFEN, 0x1},
-	{OP_WR, CCM_REG_PBF_IFEN, 0x1},
-	{OP_WR, CCM_REG_CDU_AG_WR_IFEN, 0x1},
-	{OP_WR, CCM_REG_CDU_AG_RD_IFEN, 0x1},
-	{OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1},
-	{OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1},
-	{OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1},
-#define CCM_COMMON_END          596
-#define CCM_FUNC0_START         596
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x9},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0xa},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x7},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x7},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0xc},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0xb},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x7},
-#define CCM_FUNC0_END           603
-#define CCM_FUNC1_START         603
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x29},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x27},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x27},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x2c},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x2b},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x27},
-#define CCM_FUNC1_END           610
-#define CCM_FUNC2_START         610
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x19},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x1a},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x17},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x17},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x1c},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x1b},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x17},
-#define CCM_FUNC2_END           617
-#define CCM_FUNC3_START         617
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x39},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x3a},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x37},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x37},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x3c},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x3b},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x37},
-#define CCM_FUNC3_END           624
-#define CCM_FUNC4_START         624
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x49},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x4a},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x47},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x47},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x4c},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x4b},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x47},
-#define CCM_FUNC4_END           631
-#define CCM_FUNC5_START         631
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x69},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x6a},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x67},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x67},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x6c},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x6b},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x67},
-#define CCM_FUNC5_END           638
-#define CCM_FUNC6_START         638
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x59},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x5a},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x57},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x57},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x5c},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x5b},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x57},
-#define CCM_FUNC6_END           645
-#define CCM_FUNC7_START         645
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x79},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x7a},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x77},
-	{OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x77},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x7c},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x7b},
-	{OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x77},
-#define CCM_FUNC7_END           652
-#define UCM_COMMON_START        652
-	{OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32},
-	{OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020},
-	{OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020},
-	{OP_WR, UCM_REG_TM_UCM_HDR, 0x30},
-	{OP_WR, UCM_REG_ERR_UCM_HDR, 0x8100000},
-	{OP_WR, UCM_REG_ERR_EVNT_ID, 0x33},
-	{OP_WR, UCM_REG_EXPR_EVNT_ID, 0x30},
-	{OP_WR, UCM_REG_STOP_EVNT_ID, 0x31},
-	{OP_WR, UCM_REG_STORM_WEIGHT, 0x2},
-	{OP_WR, UCM_REG_TSEM_WEIGHT, 0x4},
-	{OP_WR, UCM_REG_CSEM_WEIGHT, 0x0},
-	{OP_WR, UCM_REG_XSEM_WEIGHT, 0x2},
-	{OP_WR, UCM_REG_DORQ_WEIGHT, 0x2},
-	{OP_WR, UCM_REG_CP_WEIGHT, 0x0},
-	{OP_WR, UCM_REG_USDM_WEIGHT, 0x2},
-	{OP_WR, UCM_REG_UQM_P_WEIGHT, 0x7},
-	{OP_WR, UCM_REG_UQM_S_WEIGHT, 0x2},
-	{OP_WR, UCM_REG_TM_WEIGHT, 0x2},
-	{OP_WR, UCM_REG_UCM_UQM_USE_Q, 0x1},
-	{OP_WR, UCM_REG_INV_CFLG_Q, 0x1},
-	{OP_WR, UCM_REG_GR_ARB_TYPE, 0x1},
-	{OP_WR, UCM_REG_GR_LD0_PR, 0x1},
-	{OP_WR, UCM_REG_GR_LD1_PR, 0x2},
-	{OP_WR, UCM_REG_CFC_INIT_CRD, 0x1},
-	{OP_WR, UCM_REG_FIC0_INIT_CRD, 0x40},
-	{OP_WR, UCM_REG_FIC1_INIT_CRD, 0x40},
-	{OP_WR, UCM_REG_TM_INIT_CRD, 0x4},
-	{OP_WR, UCM_REG_UQM_INIT_CRD, 0x20},
-	{OP_WR, UCM_REG_XX_INIT_CRD, 0xe},
-	{OP_WR, UCM_REG_XX_MSG_NUM, 0x1b},
-	{OP_ZR, UCM_REG_XX_TABLE, 0x12},
-	{OP_SW_E1, UCM_REG_XX_DESCR_TABLE, 0x1b0266},
-	{OP_SW_E1H, UCM_REG_XX_DESCR_TABLE, 0x1b02a0},
-	{OP_WR, UCM_REG_N_SM_CTX_LD_0, 0x10},
-	{OP_WR, UCM_REG_N_SM_CTX_LD_1, 0x7},
-	{OP_WR, UCM_REG_N_SM_CTX_LD_2, 0xf},
-	{OP_WR, UCM_REG_N_SM_CTX_LD_3, 0x10},
-	{OP_ZR_E1, UCM_REG_N_SM_CTX_LD_4, 0x4},
-	{OP_WR_E1H, UCM_REG_N_SM_CTX_LD_4, 0xb},
-	{OP_ZR_E1H, UCM_REG_N_SM_CTX_LD_5, 0x3},
-	{OP_WR, UCM_REG_UCM_REG0_SZ, 0x3},
-	{OP_WR_E1, UCM_REG_PHYS_QNUM0_0, 0xf},
-	{OP_WR_E1, UCM_REG_PHYS_QNUM0_1, 0x2f},
-	{OP_WR_E1, UCM_REG_PHYS_QNUM1_0, 0xe},
-	{OP_WR_E1, UCM_REG_PHYS_QNUM1_1, 0x2e},
-	{OP_WR, UCM_REG_UCM_STORM0_IFEN, 0x1},
-	{OP_WR, UCM_REG_UCM_STORM1_IFEN, 0x1},
-	{OP_WR, UCM_REG_UCM_UQM_IFEN, 0x1},
-	{OP_WR, UCM_REG_STORM_UCM_IFEN, 0x1},
-	{OP_WR, UCM_REG_UQM_UCM_IFEN, 0x1},
-	{OP_WR, UCM_REG_USDM_IFEN, 0x1},
-	{OP_WR, UCM_REG_TM_UCM_IFEN, 0x1},
-	{OP_WR, UCM_REG_UCM_TM_IFEN, 0x1},
-	{OP_WR, UCM_REG_TSEM_IFEN, 0x1},
-	{OP_WR, UCM_REG_CSEM_IFEN, 0x1},
-	{OP_WR, UCM_REG_XSEM_IFEN, 0x1},
-	{OP_WR, UCM_REG_DORQ_IFEN, 0x1},
-	{OP_WR, UCM_REG_CDU_AG_WR_IFEN, 0x1},
-	{OP_WR, UCM_REG_CDU_AG_RD_IFEN, 0x1},
-	{OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1},
-	{OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1},
-	{OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1},
-#define UCM_COMMON_END          714
-#define UCM_FUNC0_START         714
-	{OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0xf},
-	{OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0xe},
-	{OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0},
-	{OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0},
-#define UCM_FUNC0_END           718
-#define UCM_FUNC1_START         718
-	{OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x2f},
-	{OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x2e},
-	{OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0},
-	{OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0},
-#define UCM_FUNC1_END           722
-#define UCM_FUNC2_START         722
-	{OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x1f},
-	{OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x1e},
-	{OP_W