diff options
| author | Dave Airlie <airlied@redhat.com> | 2013-07-30 09:43:28 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2013-07-30 09:43:28 +1000 |
| commit | 782cf7d84a723c93f05c29ce2a2a03e56427fa5b (patch) | |
| tree | 7dad0ecafc38d22ff269666e8f53ca970880f220 /drivers/gpu/drm/radeon/evergreen_hdmi.c | |
| parent | 5ae90d8e467e625e447000cb4335c4db973b1095 (diff) | |
| parent | 63f22d0e98cf74adf4ecfb25099607239b00c751 (diff) | |
Merge branch 'drm-fixes-3.11' of git://people.freedesktop.org/~agd5f/linux
Alex writes:
A few more radeon bug fixes, mostly for SI dpm. At this point dpm is
pretty solid across the majority of asics. I think we mostly just have
corner cases and fixing up some of the trickier features at this point.
* 'drm-fixes-3.11' of git://people.freedesktop.org/~agd5f/linux:
drm/radeon/dpm: fix and enable reclocking on SI
drm/radeon/dpm: disable cac setup on SI
drm/radeon/si: disable cgcg and pg for now
drm/radeon/dpm: fix forcing performance state to low on cayman
drm/radeon/atom: fix fb when fetching engine params
drm/radeon: properly handle cg on asics without UVD
drm/radeon/dpm: fix powertune handling for pci id 0x6835
drm/radeon/dpm: fix si_calculate_memory_refresh_rate()
drm/radeon/dpm: fix display gap programming on SI
drm/radeon: fix audio dto programming on DCE4+
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen_hdmi.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen_hdmi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c index b0d3fb34141..bb9ea364131 100644 --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c @@ -157,9 +157,9 @@ static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator */ + WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); - WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); } |