diff options
| author | Dave Airlie <airlied@redhat.com> | 2013-10-07 10:04:59 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2013-10-07 10:04:59 +1000 |
| commit | 12444d5f59d42158c13eca6ed8cb4292aaa4be3c (patch) | |
| tree | c43c5b292cadd670cc308a8cb8f4ddb12f151b27 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | d0e639c9e06d44e713170031fe05fb60ebe680af (diff) | |
| parent | c9976dcf55c8aaa7037427b239f15e5acfc01a3a (diff) | |
Merge tag 'drm-intel-fixes-2013-10-07' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes
Daniel writes:
Just a few important fixes, all cc: stable (I've checked this time around
and made sure they're really there ...). The dpms one is a regression from
the modeset rework and has a good chance to rectify Linus' hdmi issues.
* tag 'drm-intel-fixes-2013-10-07' of git://people.freedesktop.org/~danvet/drm-intel:
drm/i915: Only apply DPMS to the encoder if enabled
drm/i915: Mask LPSP to get PSR working even with Power Well in use by audio.
drm/i915/hsw: Disable L3 caching of atomic memory operations.
drm/i915: fix rps.vlv_work initialization
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index dd176b7296c..f4c5e95b2d6 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3864,8 +3864,6 @@ static void valleyview_enable_rps(struct drm_device *dev) dev_priv->rps.rpe_delay), dev_priv->rps.rpe_delay); - INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work); - valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); gen6_enable_rps_interrupts(dev); @@ -4955,6 +4953,11 @@ static void haswell_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); + /* L3 caching of data atomics doesn't work -- disable it. */ + I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); + I915_WRITE(HSW_ROW_CHICKEN3, + _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); + /* This is required by WaCatErrorRejectionIssue:hsw */ I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | @@ -5681,5 +5684,7 @@ void intel_pm_init(struct drm_device *dev) INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, intel_gen6_powersave_work); + + INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work); } |