Ported over SATA and DMA drivers and configsHEADmybooklive-amatus

This kernel+dtb boots on my My Book Live and
is able to access the SATA hard drive.

1 files changed, 3041 insertions, 0 deletions

diff --git a/drivers/ata/sata_dwc_pmp.c b/drivers/ata/sata_dwc_pmp.c
new file mode 100644
index 00000000000..3ff190af8d2
--- /dev/null
+++ b/drivers/ata/sata_dwc_pmp.c
@@ -0,0 +1,3041 @@
+/*
+ * drivers/ata/sata_dwc.c
+ *
+ * Synopsys DesignWare Cores (DWC) SATA host driver
+ *
+ * Author: Mark Miesfeld <mmiesfeld@amcc.com>
+ *
+ * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
+ * Copyright 2008 DENX Software Engineering
+ *
+ * Based on versions provided by AMCC and Synopsys which are:
+ *          Copyright 2006 Applied Micro Circuits Corporation
+ *          COPYRIGHT (C) 2005  SYNOPSYS, INC.  ALL RIGHTS RESERVED
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/libata.h>
+#include <linux/rtc.h>
+
+#include <scsi/scsi_host.h>
+#include <scsi/scsi_cmnd.h>
+
+
+#ifdef CONFIG_SATA_DWC_DEBUG
+#define dwc_dev_dbg(dev, format, arg...) \
+	({ if (0) dev_printk(KERN_INFO, dev, format, ##arg); 0; })
+#define dwc_port_dbg(ap, format, arg...) \
+	ata_port_printk(ap, KERN_INFO, format, ##arg)
+#define dwc_link_dbg(link, format, arg...) \
+	ata_link_printk(link, KERN_INFO, format, ##arg)
+#else
+#define dwc_dev_dbg(dev, format, arg...) \
+	({ 0; })
+#define dwc_port_dbg(ap, format, arg...) \
+	({ 0; })
+#define dwc_link_dbg(link, format, arg...) \
+	({ 0; })
+#endif
+
+#ifdef CONFIG_SATA_DWC_VDEBUG
+#define DEBUG_NCQ
+#define dwc_dev_vdbg(dev, format, arg...) \
+	({ if (0) dev_printk(KERN_INFO, dev, format, ##arg); 0; })
+#define dwc_port_vdbg(ap, format, arg...) \
+	ata_port_printk(ap, KERN_INFO, format, ##arg)
+#define dwc_link_vdbg(link, format, arg...) \
+	ata_link_printk(link, KERN_INFO, format, ##arg)
+#else
+#define dwc_dev_vdbg(dev, format, arg...) \
+	({ 0; })
+#define dwc_port_vdbg(ap, format, arg...) \
+	({ 0; })
+#define dwc_link_vdbg(link, format, arg...) \
+	({ 0; })
+#endif
+
+#define dwc_dev_info(dev, format, arg...) \
+	({ if (0) dev_printk(KERN_INFO, dev, format, ##arg); 0; })
+#define dwc_port_info(ap, format, arg...) \
+	ata_port_printk(ap, KERN_INFO, format, ##arg)
+#define dwc_link_info(link, format, arg...) \
+	ata_link_printk(link, KERN_INFO, format, ##arg)
+
+/* These two are defined in "libata.h" */
+#undef DRV_NAME
+#undef DRV_VERSION
+#define DRV_NAME        "sata-dwc"
+#define DRV_VERSION     "2.0"
+
+/* Port Multiplier discovery Signature */
+#define PSCR_SCONTROL_DET_ENABLE	0x00000001
+#define PSCR_SSTATUS_DET_PRESENT	0x00000001
+#define PSCR_SERROR_DIAG_X		0x04000000
+
+/* Port multiplier port entry in SCONTROL register */
+#define SCONTROL_PMP_MASK		0x000f0000
+#define PMP_TO_SCONTROL(p)		((p << 16) & 0x000f0000)
+#define SCONTROL_TO_PMP(p)		(((p) & 0x000f0000) >> 16)
+
+
+/* SATA DMA driver Globals */
+#if defined(CONFIG_APM821xx)
+#define DMA_NUM_CHANS			2
+#else
+#define DMA_NUM_CHANS			1
+#endif
+
+#define DMA_NUM_CHAN_REGS		8
+
+/* SATA DMA Register definitions */
+#if defined(CONFIG_APM821xx)
+#define AHB_DMA_BRST_DFLT       64  /* 16 data items burst length */
+#else
+#define AHB_DMA_BRST_DFLT		64	/* 16 data items burst length */
+#endif
+
+#if defined(CONFIG_APOLLO3G)
+extern void signal_hdd_led(int, int);
+#endif
+struct dmareg {
+	u32 low;		/* Low bits 0-31 */
+	u32 high;		/* High bits 32-63 */
+};
+
+/* DMA Per Channel registers */
+
+struct dma_chan_regs {
+	struct dmareg sar;	/* Source Address */
+	struct dmareg dar;	/* Destination address */
+	struct dmareg llp;	/* Linked List Pointer */
+	struct dmareg ctl;	/* Control */
+	struct dmareg sstat;	/* Source Status not implemented in core */
+	struct dmareg dstat;	/* Destination Status not implemented in core */
+	struct dmareg sstatar;	/* Source Status Address not impl in core */
+	struct dmareg dstatar;	/* Destination Status Address not implemented */
+	struct dmareg cfg;	/* Config */
+	struct dmareg sgr;	/* Source Gather */
+	struct dmareg dsr;	/* Destination Scatter */
+};
+
+/* Generic Interrupt Registers */
+struct dma_interrupt_regs {
+	struct dmareg tfr;	/* Transfer Interrupt */
+	struct dmareg block;	/* Block Interrupt */
+	struct dmareg srctran;	/* Source Transfer Interrupt */
+	struct dmareg dsttran;	/* Dest Transfer Interrupt */
+	struct dmareg error;	/* Error */
+};
+
+struct ahb_dma_regs {
+	struct dma_chan_regs	chan_regs[DMA_NUM_CHAN_REGS];
+	struct dma_interrupt_regs interrupt_raw;	/* Raw Interrupt */
+	struct dma_interrupt_regs interrupt_status;	/* Interrupt Status */
+	struct dma_interrupt_regs interrupt_mask;	/* Interrupt Mask */
+	struct dma_interrupt_regs interrupt_clear;	/* Interrupt Clear */
+	struct dmareg		statusInt;		/* Interrupt combined */
+	struct dmareg		rq_srcreg;		/* Src Trans Req */
+	struct dmareg		rq_dstreg;		/* Dst Trans Req */
+	struct dmareg		rq_sgl_srcreg;		/* Sngl Src Trans Req */
+	struct dmareg		rq_sgl_dstreg;		/* Sngl Dst Trans Req */
+	struct dmareg		rq_lst_srcreg;		/* Last Src Trans Req */
+	struct dmareg		rq_lst_dstreg;		/* Last Dst Trans Req */
+	struct dmareg		dma_cfg;		/* DMA Config */
+	struct dmareg		dma_chan_en;		/* DMA Channel Enable */
+	struct dmareg		dma_id;			/* DMA ID */
+	struct dmareg		dma_test;		/* DMA Test */
+	struct dmareg		res1;			/* reserved */
+	struct dmareg		res2;			/* reserved */
+
+	/* DMA Comp Params
+	 * Param 6 = dma_param[0], Param 5 = dma_param[1],
+	 * Param 4 = dma_param[2] ...
+	 */
+	struct dmareg		dma_params[6];
+};
+
+/* Data structure for linked list item */
+struct lli {
+	u32		sar;		/* Source Address */
+	u32		dar;		/* Destination address */
+	u32		llp;		/* Linked List Pointer */
+	struct dmareg	ctl;		/* Control */
+#if defined(CONFIG_APM821xx)
+	u32             dstat;          /* Source status is not supported */
+#else
+	struct dmareg	dstat;		/* Destination Status */
+#endif
+};
+
+#define SATA_DWC_DMAC_LLI_SZ		(sizeof(struct lli))
+#define SATA_DWC_DMAC_LLI_NUM		256
+#define SATA_DWC_DMAC_TWIDTH_BYTES	4
+#define SATA_DWC_DMAC_LLI_TBL_SZ	\
+	(SATA_DWC_DMAC_LLI_SZ * SATA_DWC_DMAC_LLI_NUM)
+#if defined(CONFIG_APM821xx)
+#define SATA_DWC_DMAC_CTRL_TSIZE_MAX    \
+        (0x00000800 * SATA_DWC_DMAC_TWIDTH_BYTES)
+#else
+#define SATA_DWC_DMAC_CTRL_TSIZE_MAX	\
+	(0x00000800 * SATA_DWC_DMAC_TWIDTH_BYTES)
+#endif
+/* DMA Register Operation Bits */
+#define DMA_EN              0x00000001		/* Enable AHB DMA */
+#define DMA_CHANNEL(ch)		(0x00000001 << (ch))	/* Select channel */
+#define DMA_ENABLE_CHAN(ch)	((0x00000001 << (ch)) |			\
+				 ((0x000000001 << (ch)) << 8))
+#define DMA_DISABLE_CHAN(ch)	(0x00000000 | ((0x000000001 << (ch)) << 8))
+
+/* Channel Control Register */
+#define DMA_CTL_BLK_TS(size)	((size) & 0x000000FFF)	/* Blk Transfer size */
+#define DMA_CTL_LLP_SRCEN	0x10000000	/* Blk chain enable Src */
+#define DMA_CTL_LLP_DSTEN	0x08000000	/* Blk chain enable Dst */
+/*
+ * This define is used to set block chaining disabled in the control low
+ * register.  It is already in little endian format so it can be &'d dirctly.
+ * It is essentially: cpu_to_le32(~(DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN))
+ */
+#define DMA_CTL_LLP_DISABLE_LE32 0xffffffe7
+#define DMA_CTL_SMS(num)	((num & 0x3) << 25)	/*Src Master Select*/
+#define DMA_CTL_DMS(num)	((num & 0x3) << 23)	/*Dst Master Select*/
+#define DMA_CTL_TTFC(type)	((type & 0x7) << 20)	/*Type&Flow cntr*/
+#define DMA_CTL_TTFC_P2M_DMAC	0x00000002		/*Per mem,DMAC cntr*/
+#define DMA_CTL_TTFC_M2P_PER	0x00000003		/*Mem per,peri cntr*/
+#define DMA_CTL_SRC_MSIZE(size)	((size & 0x7) << 14)	/*Src Burst Len*/
+#define DMA_CTL_DST_MSIZE(size)	((size & 0x7) << 11)	/*Dst Burst Len*/
+#define DMA_CTL_SINC_INC	0x00000000		/*Src addr incr*/
+#define DMA_CTL_SINC_DEC	0x00000200
+#define DMA_CTL_SINC_NOCHANGE	0x00000400
+#define DMA_CTL_DINC_INC	0x00000000		/*Dst addr incr*/
+#define DMA_CTL_DINC_DEC	0x00000080
+#define DMA_CTL_DINC_NOCHANGE	0x00000100
+#define DMA_CTL_SRC_TRWID(size)	((size & 0x7) << 4)	/*Src Trnsfr Width*/
+#define DMA_CTL_DST_TRWID(size)	((size & 0x7) << 1)	/*Dst Trnsfr Width*/
+#define DMA_CTL_INT_EN		0x00000001		/*Interrupt Enable*/
+
+/* Channel Configuration Register high bits */
+#define DMA_CFG_FCMOD_REQ	0x00000001		/*Flow cntrl req*/
+#define DMA_CFG_PROTCTL		(0x00000003 << 2)	/*Protection cntrl*/
+
+/* Channel Configuration Register low bits */
+#define DMA_CFG_RELD_DST	0x80000000		/*Reload Dst/Src Addr*/
+#define DMA_CFG_RELD_SRC	0x40000000
+#define DMA_CFG_HS_SELSRC	0x00000800		/*SW hndshk Src/Dst*/
+#define DMA_CFG_HS_SELDST	0x00000400
+#define DMA_CFG_FIFOEMPTY       (0x00000001 << 9)	/*FIFO Empty bit*/
+
+/* Assign hardware handshaking interface (x) to dst / sre peripheral */
+#define DMA_CFG_HW_HS_DEST(int_num)	((int_num & 0xF) << 11)
+#define DMA_CFG_HW_HS_SRC(int_num)	((int_num & 0xF) << 7)
+
+/* Channel Linked List Pointer Register */
+#define DMA_LLP_LMS(addr, master)	(((addr) & 0xfffffffc) | (master))
+#define DMA_LLP_AHBMASTER1		0	/* List Master Select */
+#define DMA_LLP_AHBMASTER2		1
+
+#define SATA_DWC_MAX_PORTS	1
+
+#define SATA_DWC_SCR_OFFSET	0x24
+#define SATA_DWC_REG_OFFSET	0x64
+
+/* DWC SATA Registers */
+struct sata_dwc_regs {
+	u32 fptagr;		/* 1st party DMA tag */
+	u32 fpbor;		/* 1st party DMA buffer offset */
+	u32 fptcr;		/* 1st party DMA Xfr count */
+	u32 dmacr;		/* DMA Control */
+	u32 dbtsr;		/* DMA Burst Transac size */
+	u32 intpr;		/* Interrupt Pending */
+	u32 intmr;		/* Interrupt Mask */
+	u32 errmr;		/* Error Mask */
+	u32 llcr;		/* Link Layer Control */
+	u32 phycr;		/* PHY Control */
+	u32 physr;		/* PHY Status */
+	u32 rxbistpd;		/* Recvd BIST pattern def register */
+	u32 rxbistpd1;		/* Recvd BIST data dword1 */
+	u32 rxbistpd2;		/* Recvd BIST pattern data dword2 */
+	u32 txbistpd;		/* Trans BIST pattern def register */
+	u32 txbistpd1;		/* Trans BIST data dword1 */
+	u32 txbistpd2;		/* Trans BIST data dword2 */
+	u32 bistcr;		/* BIST Control Register */
+	u32 bistfctr;		/* BIST FIS Count Register */
+	u32 bistsr;		/* BIST Status Register */
+	u32 bistdecr;		/* BIST Dword Error count register */
+	u32 res[15];		/* Reserved locations */
+	u32 testr;		/* Test Register */
+	u32 versionr;		/* Version Register */
+	u32 idr;		/* ID Register */
+	u32 unimpl[192];	/* Unimplemented */
+	u32 dmadr[256];	/* FIFO Locations in DMA Mode */
+};
+
+#define SCR_SCONTROL_DET_ENABLE		0x00000001
+#define SCR_SSTATUS_DET_PRESENT		0x00000001
+#define SCR_SERROR_DIAG_X		0x04000000
+
+/* DWC SATA Register Operations */
+#define	SATA_DWC_TXFIFO_DEPTH		0x01FF
+#define	SATA_DWC_RXFIFO_DEPTH		0x01FF
+
+#define SATA_DWC_DMACR_TMOD_TXCHEN	0x00000004
+#define	SATA_DWC_DMACR_TXCHEN		(0x00000001 | \
+						SATA_DWC_DMACR_TMOD_TXCHEN)
+#define	SATA_DWC_DMACR_RXCHEN		(0x00000002 | \
+						SATA_DWC_DMACR_TMOD_TXCHEN)
+#define SATA_DWC_DMACR_TX_CLEAR(v)	(((v) & ~SATA_DWC_DMACR_TXCHEN) | \
+						SATA_DWC_DMACR_TMOD_TXCHEN)
+#define SATA_DWC_DMACR_RX_CLEAR(v)	(((v) & ~SATA_DWC_DMACR_RXCHEN) | \
+						SATA_DWC_DMACR_TMOD_TXCHEN)
+#define SATA_DWC_DMACR_TXRXCH_CLEAR	SATA_DWC_DMACR_TMOD_TXCHEN
+
+#define SATA_DWC_DBTSR_MWR(size)	((size/4) & \
+						SATA_DWC_TXFIFO_DEPTH)
+#define SATA_DWC_DBTSR_MRD(size)	(((size/4) & \
+						SATA_DWC_RXFIFO_DEPTH) << 16)
+
+// SATA DWC Interrupts
+#define	SATA_DWC_INTPR_DMAT			0x00000001
+#define SATA_DWC_INTPR_NEWFP		0x00000002
+#define SATA_DWC_INTPR_PMABRT		0x00000004
+#define SATA_DWC_INTPR_ERR			0x00000008
+#define SATA_DWC_INTPR_NEWBIST		0x00000010
+#define SATA_DWC_INTPR_IPF			0x80000000
+// Interrupt masks
+#define	SATA_DWC_INTMR_DMATM		0x00000001
+#define SATA_DWC_INTMR_NEWFPM		0x00000002
+#define SATA_DWC_INTMR_PMABRTM		0x00000004
+#define SATA_DWC_INTMR_ERRM			0x00000008
+#define SATA_DWC_INTMR_NEWBISTM		0x00000010
+#define SATA_DWC_INTMR_PRIMERRM		0x00000020
+#define SATA_DWC_INTPR_CMDGOOD		0x00000080
+#define SATA_DWC_INTPR_CMDABORT		0x00000040
+
+#define SATA_DWC_LLCR_SCRAMEN		0x00000001
+#define SATA_DWC_LLCR_DESCRAMEN		0x00000002
+#define SATA_DWC_LLCR_RPDEN			0x00000004
+
+// Defines for SError register
+#define SATA_DWC_SERR_ERRI      0x00000001 // Recovered data integrity error
+#define SATA_DWC_SERR_ERRM      0x00000002 // Recovered communication error
+#define SATA_DWC_SERR_ERRT      0x00000100 // Non-recovered transient data integrity error
+#define SATA_DWC_SERR_ERRC      0x00000200 // Non-recovered persistent communication or data integrity error
+#define SATA_DWC_SERR_ERRP      0x00000400 // Protocol error
+#define SATA_DWC_SERR_ERRE      0x00000800 // Internal host adapter error
+#define SATA_DWC_SERR_DIAGN     0x00010000 // PHYRdy change
+#define SATA_DWC_SERR_DIAGI     0x00020000 // PHY internal error
+#define SATA_DWC_SERR_DIAGW     0x00040000 // Phy COMWAKE signal is detected
+#define SATA_DWC_SERR_DIAGB     0x00080000 // 10b to 8b decoder err
+#define SATA_DWC_SERR_DIAGT     0x00100000 // Disparity error
+#define SATA_DWC_SERR_DIAGC		0x00200000 // CRC error
+#define SATA_DWC_SERR_DIAGH		0x00400000 // Handshake error
+#define SATA_DWC_SERR_DIAGL		0x00800000 // Link sequence (illegal transition) error
+#define SATA_DWC_SERR_DIAGS		0x01000000 // Transport state transition error
+#define SATA_DWC_SERR_DIAGF		0x02000000 // Unrecognized FIS type
+#define SATA_DWC_SERR_DIAGX		0x04000000 // Exchanged error - Set when PHY COMINIT signal is detected.
+#define SATA_DWC_SERR_DIAGA		0x08000000 // Port Selector Presence detected
+
+/* This is all error bits, zero's are reserved fields. */
+#define SATA_DWC_SERR_ERR_BITS	0x0FFF0F03
+
+#define SATA_DWC_SCR0_SPD_GET(v)	((v >> 4) & 0x0000000F)
+
+struct sata_dwc_device {
+	struct resource reg;            /* Resource for register */
+	struct device		*dev;		/* generic device struct */
+	struct ata_probe_ent	*pe;		/* ptr to probe-ent */
+	struct ata_host		*host;
+	u8			*reg_base;
+	struct sata_dwc_regs	*sata_dwc_regs;	/* DW Synopsys SATA specific */
+	u8     			*scr_base;
+	int    			dma_channel;	/* DWC SATA DMA channel  */
+	int			irq_dma;
+	struct timer_list an_timer;
+};
+
+#define SATA_DWC_QCMD_MAX	32
+
+struct sata_dwc_device_port {
+	struct sata_dwc_device	*hsdev;
+	int			cmd_issued[SATA_DWC_QCMD_MAX];
+	struct lli		*llit[SATA_DWC_QCMD_MAX];
+	dma_addr_t		llit_dma[SATA_DWC_QCMD_MAX];
+	u32			dma_chan[SATA_DWC_QCMD_MAX];
+	int			dma_pending[SATA_DWC_QCMD_MAX];
+	u32 			sata_dwc_sactive_issued;	/* issued queued ops */
+	u32 			sata_dwc_sactive_queued;	/* queued ops */
+	u32 			dma_interrupt_count;
+
+};
+
+static struct sata_dwc_device* dwc_dev_list[2];
+static int dma_intr_registered = 0;
+/*
+ * Commonly used DWC SATA driver Macros
+ */
+#define HSDEV_FROM_HOST(host)	((struct sata_dwc_device *) \
+					(host)->private_data)
+#define HSDEV_FROM_AP(ap)	((struct sata_dwc_device *) \
+					(ap)->host->private_data)
+#define HSDEVP_FROM_AP(ap)	((struct sata_dwc_device_port *) \
+					(ap)->private_data)
+#define HSDEV_FROM_QC(qc)	((struct sata_dwc_device *) \
+					(qc)->ap->host->private_data)
+#define HSDEV_FROM_HSDEVP(p)	((struct sata_dwc_device *) \
+					(hsdevp)->hsdev)
+
+enum {
+	SATA_DWC_CMD_ISSUED_NOT		= 0,
+	SATA_DWC_CMD_ISSUED_PENDING	= 1,
+	SATA_DWC_CMD_ISSUED_EXEC	= 2,
+	SATA_DWC_CMD_ISSUED_NODATA	= 3,
+
+	SATA_DWC_DMA_PENDING_NONE	= 0,
+	SATA_DWC_DMA_PENDING_TX		= 1,
+	SATA_DWC_DMA_PENDING_RX		= 2,
+};
+
+/*
+ * Globals
+ */
+static struct ahb_dma_regs *sata_dma_regs = 0;
+
+/*
+ * Prototypes
+ */
+static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
+static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
+				u32 check_status);
+static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
+static void sata_dwc_port_stop(struct ata_port *ap);
+static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
+
+static int dma_dwc_init(struct sata_dwc_device *hsdev);
+static void dma_dwc_exit(struct sata_dwc_device *hsdev);
+static int dma_dwc_xfer_setup(struct ata_queued_cmd *qc,
+			      struct lli *lli, dma_addr_t dma_lli,
+			      void __iomem *addr);
+static void dma_dwc_xfer_start(int dma_ch);
+static void dma_dwc_terminate_dma(struct ata_port *ap, int dma_ch);
+static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev);
+static void sata_dwc_init_port ( struct ata_port *ap );
+u8 sata_dwc_check_status(struct ata_port *ap);
+
+
+
+
+static const char *dir_2_txt(enum dma_data_direction dir)
+{
+	switch (dir) {
+	case DMA_BIDIRECTIONAL:
+		return "bi";
+	case DMA_FROM_DEVICE:
+		return "from";
+	case DMA_TO_DEVICE:
+		return "to";
+	case DMA_NONE:
+		return "none";
+	default:
+		return "err";
+	}
+}
+
+static const char *prot_2_txt(enum ata_tf_protocols protocol)
+{
+	switch (protocol) {
+	case ATA_PROT_UNKNOWN:
+		return "unknown";
+	case ATA_PROT_NODATA:
+		return "nodata";
+	case ATA_PROT_PIO:
+		return "pio";
+	case ATA_PROT_DMA:
+		return "dma";
+	case ATA_PROT_NCQ:
+		return "ncq";
+	case ATAPI_PROT_PIO:
+		return "atapi pio";
+	case ATAPI_PROT_NODATA:
+		return "atapi nodata";
+	case ATAPI_PROT_DMA:
+		return "atapi dma";
+	default:
+		return "err";
+	}
+}
+
+inline const char *ata_cmd_2_txt(const struct ata_taskfile *tf)
+{
+	switch (tf->command) {
+	case ATA_CMD_CHK_POWER:
+		return "ATA_CMD_CHK_POWER";
+	case ATA_CMD_EDD:
+		return "ATA_CMD_EDD";
+	case ATA_CMD_FLUSH:
+		return "ATA_CMD_FLUSH";
+	case ATA_CMD_FLUSH_EXT:
+		return "ATA_CMD_FLUSH_EXT";
+	case ATA_CMD_ID_ATA:
+		return "ATA_CMD_ID_ATA";
+	case ATA_CMD_ID_ATAPI:
+		return "ATA_CMD_ID_ATAPI";
+	case ATA_CMD_FPDMA_READ:
+		return "ATA_CMD_FPDMA_READ";
+	case ATA_CMD_FPDMA_WRITE:
+		return "ATA_CMD_FPDMA_WRITE";
+	case ATA_CMD_READ:
+		return "ATA_CMD_READ";
+	case ATA_CMD_READ_EXT:
+		return "ATA_CMD_READ_EXT";
+	case ATA_CMD_READ_NATIVE_MAX_EXT :
+		return "ATA_CMD_READ_NATIVE_MAX_EXT";
+	case ATA_CMD_VERIFY_EXT :
+		return "ATA_CMD_VERIFY_EXT";
+	case ATA_CMD_WRITE:
+		return "ATA_CMD_WRITE";
+	case ATA_CMD_WRITE_EXT:
+		return "ATA_CMD_WRITE_EXT";
+	case ATA_CMD_PIO_READ:
+		return "ATA_CMD_PIO_READ";
+	case ATA_CMD_PIO_READ_EXT:
+		return "ATA_CMD_PIO_READ_EXT";
+	case ATA_CMD_PIO_WRITE:
+		return "ATA_CMD_PIO_WRITE";
+	case ATA_CMD_PIO_WRITE_EXT:
+		return "ATA_CMD_PIO_WRITE_EXT";
+	case ATA_CMD_SET_FEATURES:
+		return "ATA_CMD_SET_FEATURES";
+	case ATA_CMD_PACKET:
+		return "ATA_CMD_PACKET";
+	case ATA_CMD_PMP_READ:
+		return "ATA_CMD_PMP_READ";
+	case ATA_CMD_PMP_WRITE:
+		return "ATA_CMD_PMP_WRITE";
+	default:
+		return "ATA_CMD_???";
+	}
+}
+
+/* 
+ * Dump content of the taskfile
+ */
+static void sata_dwc_tf_dump(struct device *dwc_dev, struct ata_taskfile *tf)
+{
+	dwc_dev_vdbg(dwc_dev, "taskfile cmd: 0x%02x protocol: %s flags: 0x%lx"
+			"device: %x\n", tf->command, prot_2_txt(tf->protocol),
+			tf->flags, tf->device);
+	dwc_dev_vdbg(dwc_dev, "feature: 0x%02x nsect: 0x%x lbal: 0x%x lbam:"
+			"0x%x lbah: 0x%x\n", tf->feature, tf->nsect, tf->lbal,
+			tf->lbam, tf->lbah);
+	dwc_dev_vdbg(dwc_dev, "hob_feature: 0x%02x hob_nsect: 0x%x hob_lbal: 0x%x "
+			"hob_lbam: 0x%x hob_lbah: 0x%x\n", tf->hob_feature,
+			tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
+			tf->hob_lbah);
+}
+
+/*
+ * Function: get_burst_length_encode
+ * arguments: datalength: length in bytes of data
+ * returns value to be programmed in register corresponding to data length
+ * This value is effectively the log(base 2) of the length
+ */
+static inline int get_burst_length_encode(int datalength)
+{
+	int items = datalength >> 2;	/* div by 4 to get lword count */
+
+	if (items >= 64)
+		return 5;
+
+	if (items >= 32)
+		return 4;
+
+	if (items >= 16)
+		return 3;
+
+	if (items >= 8)
+		return 2;
+
+	if (items >= 4)
+		return 1;
+
+	return 0;
+}
+
+/*
+ * Clear Interrupts on a DMA channel
+ */
+static inline void clear_chan_interrupts(int c)
+{
+	out_le32(&(sata_dma_regs->interrupt_clear.tfr.low), DMA_CHANNEL(c));
+	out_le32(&(sata_dma_regs->interrupt_clear.block.low), DMA_CHANNEL(c));
+	out_le32(&(sata_dma_regs->interrupt_clear.srctran.low), DMA_CHANNEL(c));
+	out_le32(&(sata_dma_regs->interrupt_clear.dsttran.low), DMA_CHANNEL(c));
+	out_le32(&(sata_dma_regs->interrupt_clear.error.low), DMA_CHANNEL(c));
+}
+
+/*
+ * Function: dma_request_channel
+ * arguments: None
+ * returns channel number if available else -1
+ * This function assigns the next available DMA channel from the list to the
+ * requester
+ */
+static int dma_request_channel(struct ata_port *ap)
+{
+	struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
+
+	if (!(in_le32(&(sata_dma_regs->dma_chan_en.low)) & DMA_CHANNEL(hsdev->dma_channel))) {
+		dwc_port_vdbg(ap, "%s Successfully requested DMA channel %d\n", 
+				__func__, hsdev->dma_channel);
+		return (hsdev->dma_channel);
+	}
+	
+	return -1;
+}
+
+
+
+/*
+ * Function: dma_dwc_interrupt
+ * arguments: irq, dev_id, pt_regs
+ * returns channel number if available else -1
+ * Interrupt Handler for DW AHB SATA DMA
+ */
+static int dma_dwc_interrupt(int irq, void *hsdev_instance)
+{
+	volatile u32 tfr_reg, err_reg;
+	unsigned long flags;
+	struct sata_dwc_device *hsdev = hsdev_instance;
+	struct ata_host *host = (struct ata_host *)hsdev->host;
+	struct ata_port *ap;
+	struct sata_dwc_device_port *hsdevp;
+	u8 tag = 0;
+	int chan;
+	unsigned int port = 0;
+	spin_lock_irqsave(&host->lock, flags);
+
+	ap = host->ports[port];
+	hsdevp = HSDEVP_FROM_AP(ap);
+	tag = ap->link.active_tag;
+
+	dwc_port_vdbg(ap, "%s: DMA interrupt in channel %d\n", __func__, hsdev->dma_channel);
+
+	tfr_reg = in_le32(&(sata_dma_regs->interrupt_status.tfr.low));
+	err_reg = in_le32(&(sata_dma_regs->interrupt_status.error.low));
+
+	dwc_port_vdbg(ap, "eot=0x%08x err=0x%08x pending=%d active port=%d\n",
+		tfr_reg, err_reg, hsdevp->dma_pending[tag], port);
+	chan = hsdev->dma_channel;				
+	
+	if (tfr_reg & DMA_CHANNEL(chan)) {
+		/*
+		 *Each DMA command produces 2 interrupts.  Only
+		 * complete the command after both interrupts have been
+		 * seen. (See sata_dwc_isr())
+		 */
+		hsdevp->dma_interrupt_count++;
+		sata_dwc_clear_dmacr(hsdevp, tag);
+
+		if (unlikely(hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE)) {
+			dev_err(ap->dev, "DMA not pending eot=0x%08x "
+				"err=0x%08x tag=0x%02x pending=%d\n",
+				tfr_reg, err_reg, tag,
+				hsdevp->dma_pending[tag]);
+		}
+
+		// Do remain jobs after DMA transfer complete
+		if ((hsdevp->dma_interrupt_count % 2) == 0)
+			sata_dwc_dma_xfer_complete(ap, 1);
+
+		/* Clear the interrupt */
+		out_le32(&(sata_dma_regs->interrupt_clear.tfr.low),
+			  DMA_CHANNEL(chan));
+	}
+
+	/* Process error interrupt. */
+	// We do not expect error happen
+	if (unlikely(err_reg & DMA_CHANNEL(chan))) {
+		/* TODO Need error handler ! */
+		dev_err(ap->dev, "error interrupt err_reg=0x%08x\n",
+				err_reg);
+
+		spin_lock_irqsave(ap->lock, flags);
+		//if (ata_is_dma(qc->tf.protocol)) {
+			/* disable DMAC */
+			dma_dwc_terminate_dma(ap, chan);
+		//}
+		spin_unlock_irqrestore(ap->lock, flags);
+
+		/* Clear the interrupt. */
+		out_le32(&(sata_dma_regs->interrupt_clear.error.low),
+			  DMA_CHANNEL(chan));
+	}
+
+	spin_unlock_irqrestore(&host->lock, flags);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t dma_dwc_handler(int irq, void *hsdev_instance)
+{
+	volatile u32 tfr_reg, err_reg;
+	int chan;
+
+	tfr_reg = in_le32(&(sata_dma_regs->interrupt_status.tfr.low));	
+	err_reg = in_le32(&(sata_dma_regs->interrupt_status.error.low));
+
+	for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
+		/* Check for end-of-transfer interrupt. */
+
+		if (tfr_reg & DMA_CHANNEL(chan)) {
+			dma_dwc_interrupt(0, dwc_dev_list[chan]);		
+		}
+		else
+
+		/* Check for error interrupt. */
+		if (err_reg & DMA_CHANNEL(chan)) {
+			dma_dwc_interrupt(0, dwc_dev_list[chan]);
+		}
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int dma_register_interrupt (struct sata_dwc_device *hsdev)
+{
+	int retval = 0;
+	int irq = hsdev->irq_dma;
+	/* 
+	 * FIXME: 2 SATA controllers share the same DMA engine so
+	 * currently, they also share same DMA interrupt
+	 */
+	if (!dma_intr_registered) {
+		printk("%s register irq (%d)\n", __func__, irq);
+		retval = request_irq(irq, dma_dwc_handler, IRQF_SHARED, "SATA DMA", hsdev);
+		//retval = request_irq(irq, dma_dwc_handler, IRQF_DISABLED, "SATA DMA", NULL);
+		if (retval) {
+			dev_err(hsdev->dev, "%s: could not get IRQ %d\n", __func__, irq);
+			return -ENODEV;
+		}
+		//dma_intr_registered = 1;
+	}
+	return retval;
+}
+
+/*
+ * Function: dma_request_interrupts
+ * arguments: hsdev
+ * returns status
+ * This function registers ISR for a particular DMA channel interrupt
+ */
+static int dma_request_interrupts(struct sata_dwc_device *hsdev, int irq)
+{
+	int retval = 0;
+	int dma_chan = hsdev->dma_channel;
+
+	/* Unmask error interrupt */
+	out_le32(&sata_dma_regs->interrupt_mask.error.low,
+			 in_le32(&sata_dma_regs->interrupt_mask.error.low) | DMA_ENABLE_CHAN(dma_chan));
+
+	/* Unmask end-of-transfer interrupt */
+	out_le32(&sata_dma_regs->interrupt_mask.tfr.low,
+			in_le32(&sata_dma_regs->interrupt_mask.tfr.low) | DMA_ENABLE_CHAN(dma_chan));
+
+	dwc_dev_vdbg(hsdev->dev, "Current value of interrupt_mask.error=0x%0x\n", in_le32(&sata_dma_regs->interrupt_mask.error.low));
+	dwc_dev_vdbg(hsdev->dev, "Current value of interrupt_mask.tfr=0x%0x\n", in_le32(&sata_dma_regs->interrupt_mask.tfr.low));
+#if 0
+	out_le32(&sata_dma_regs->interrupt_mask.block.low,
+			DMA_ENABLE_CHAN(dma_chan));
+
+	out_le32(&sata_dma_regs->interrupt_mask.srctran.low,
+			DMA_ENABLE_CHAN(dma_chan));
+
+	out_le32(&sata_dma_regs->interrupt_mask.dsttran.low,
+			DMA_ENABLE_CHAN(dma_chan));
+#endif
+	return retval;
+}
+
+/*
+ * Function: map_sg_to_lli
+ * arguments: sg: scatter/gather list(sg)
+ *	      num_elems: no of elements in sg list
+ *	      dma_lli: LLI table
+ *	      dest: destination address
+ *	      read: whether the transfer is read or write
+ * returns array of AHB DMA Linked List Items
+ * This function creates a list of LLIs for DMA Xfr and returns the number
+ * of elements in the DMA linked list.
+ *
+ * Note that the Synopsis driver has a comment proposing that better performance
+ * is possible by only enabling interrupts on the last item in the linked list.
+ * However, it seems that could be a problem if an error happened on one of the
+ * first items.  The transfer would halt, but no error interrupt would occur.
+ *
+ * Currently this function sets interrupts enabled for each linked list item:
+ * DMA_CTL_INT_EN.
+ */
+static int map_sg_to_lli(struct ata_queued_cmd *qc, struct lli *lli,
+			 dma_addr_t dma_lli, void __iomem *dmadr_addr)
+{
+	struct scatterlist *sg = qc->sg;
+	struct device *dwc_dev = qc->ap->dev;
+	int num_elems = qc->n_elem;
+	int dir = qc->dma_dir;
+	struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(qc->ap);
+	
+	int i, idx = 0;
+	int fis_len = 0;
+	dma_addr_t next_llp;
+	int bl;
+	unsigned int dma_ts = 0;
+
+	dwc_port_vdbg(qc->ap, "%s: sg=%p nelem=%d lli=%p dma_lli=0x%08x "
+		"dmadr=0x%08x\n", __func__, sg, num_elems, lli, (u32)dma_lli,
+		(u32)dmadr_addr);
+
+	bl = get_burst_length_encode(AHB_DMA_BRST_DFLT);
+
+	for (i = 0; i < num_elems; i++, sg++) {
+		u32 addr, offset;
+		u32 sg_len, len;
+
+		addr = (u32) sg_dma_address(sg);
+		sg_len = sg_dma_len(sg);
+
+		dwc_port_vdbg(qc->ap, "%s: elem=%d sg_addr=0x%x sg_len=%d\n",
+			__func__, i, addr, sg_len);
+
+		while (sg_len) {
+
+			if (unlikely(idx >= SATA_DWC_DMAC_LLI_NUM)) {
+				/* The LLI table is not large enough. */
+				dev_err(dwc_dev, "LLI table overrun (idx=%d)\n",
+						idx);
+				break;
+			}
+			len = (sg_len > SATA_DWC_DMAC_CTRL_TSIZE_MAX) ?
+				SATA_DWC_DMAC_CTRL_TSIZE_MAX : sg_len;
+
+			offset = addr & 0xffff;
+			if ((offset + sg_len) > 0x10000)
+				len = 0x10000 - offset;
+
+			/*
+			 * Make sure a LLI block is not created that will span a
+			 * 8K max FIS boundary.  If the block spans such a FIS
+			 * boundary, there is a chance that a DMA burst will
+			 * cross that boundary -- this results in an error in
+			 * the host controller.
+			 */
+			if (unlikely(fis_len + len > 8192)) {
+				dwc_port_vdbg(qc->ap, "SPLITTING: fis_len=%d(0x%x) "
+					"len=%d(0x%x)\n", fis_len, fis_len,
+					len, len);
+				len = 8192 - fis_len;
+				fis_len = 0;
+			} else {
+				fis_len += len;
+			}
+			if (fis_len == 8192)
+				fis_len = 0;
+
+			/*
+			 * Set DMA addresses and lower half of control register
+			 * based on direction.
+			 */
+			dwc_port_vdbg(qc->ap, "%s: sg_len = %d, len = %d\n", __func__, sg_len, len);
+
+#if defined(CONFIG_APM821xx)
+			 if (dir == DMA_FROM_DEVICE) {
+                                lli[idx].dar = cpu_to_le32(addr);
+                                lli[idx].sar = cpu_to_le32((u32)dmadr_addr);
+				if (hsdevp->hsdev->dma_channel == 0) {/* DMA channel 0 */
+		                        lli[idx].ctl.low = cpu_to_le32(
+                                        DMA_CTL_TTFC(DMA_CTL_TTFC_P2M_DMAC) |
+                                        DMA_CTL_SMS(1) |	/* Source: Master 2 */
+                                        DMA_CTL_DMS(0) |	/* Dest: Master 1 */
+                                        DMA_CTL_SRC_MSIZE(bl) |
+                                        DMA_CTL_DST_MSIZE(bl) |
+                                        DMA_CTL_SINC_NOCHANGE |
+                                        DMA_CTL_SRC_TRWID(2) |
+                                        DMA_CTL_DST_TRWID(2) |
+                                        DMA_CTL_INT_EN |
+                                        DMA_CTL_LLP_SRCEN |
+                                        DMA_CTL_LLP_DSTEN);
+				} else if (hsdevp->hsdev->dma_channel == 1) {/* DMA channel 1 */
+					lli[idx].ctl.low = cpu_to_le32(
+                                        DMA_CTL_TTFC(DMA_CTL_TTFC_P2M_DMAC) |
+                                        DMA_CTL_SMS(2) |	/* Source: Master 3 */
+                                        DMA_CTL_DMS(0) |	/* Dest: Master 1 */
+                                        DMA_CTL_SRC_MSIZE(bl) |
+                                        DMA_CTL_DST_MSIZE(bl) |
+                                        DMA_CTL_SINC_NOCHANGE |
+                                        DMA_CTL_SRC_TRWID(2) |
+                                        DMA_CTL_DST_TRWID(2) |
+                                        DMA_CTL_INT_EN |
+                                        DMA_CTL_LLP_SRCEN |
+                                        DMA_CTL_LLP_DSTEN);
+				}
+                        } else {        /* DMA_TO_DEVICE */
+                                lli[idx].sar = cpu_to_le32(addr);
+                                lli[idx].dar = cpu_to_le32((u32)dmadr_addr);
+				if (hsdevp->hsdev->dma_channel == 0) {/* DMA channel 0 */
+	                                lli[idx].ctl.low = cpu_to_le32(
+                                        DMA_CTL_TTFC(DMA_CTL_TTFC_M2P_PER) |
+                                        DMA_CTL_SMS(0) |
+                                        DMA_CTL_DMS(1) |
+                                        DMA_CTL_SRC_MSIZE(bl) |
+                                        DMA_CTL_DST_MSIZE(bl) |
+                                        DMA_CTL_DINC_NOCHANGE |
+                                        DMA_CTL_SRC_TRWID(2) |
+                                        DMA_CTL_DST_TRWID(2) |
+                                        DMA_CTL_INT_EN |
+                                        DMA_CTL_LLP_SRCEN |
+                                        DMA_CTL_LLP_DSTEN);
+				} else if (hsdevp->hsdev->dma_channel == 1) {/* DMA channel 1 */
+	                                lli[idx].ctl.low = cpu_to_le32(
+                                        DMA_CTL_TTFC(DMA_CTL_TTFC_M2P_PER) |
+                                        DMA_CTL_SMS(0) |
+                                        DMA_CTL_DMS(2) |
+                                        DMA_CTL_SRC_MSIZE(bl) |
+                                        DMA_CTL_DST_MSIZE(bl) |
+                                        DMA_CTL_DINC_NOCHANGE |
+                                        DMA_CTL_SRC_TRWID(2) |
+                                        DMA_CTL_DST_TRWID(2) |
+                                        DMA_CTL_INT_EN |
+                                        DMA_CTL_LLP_SRCEN |
+                                        DMA_CTL_LLP_DSTEN);
+				}
+                        }
+#else
+			if (dir == DMA_FROM_DEVICE) {
+				lli[idx].dar = cpu_to_le32(addr);
+				lli[idx].sar = cpu_to_le32((u32)dmadr_addr);
+
+				lli[idx].ctl.low = cpu_to_le32(
+					DMA_CTL_TTFC(DMA_CTL_TTFC_P2M_DMAC) |
+					DMA_CTL_SMS(0) |
+					DMA_CTL_DMS(1) |
+					DMA_CTL_SRC_MSIZE(bl) |
+					DMA_CTL_DST_MSIZE(bl) |
+					DMA_CTL_SINC_NOCHANGE |
+					DMA_CTL_SRC_TRWID(2) |
+					DMA_CTL_DST_TRWID(2) |
+					DMA_CTL_INT_EN |
+					DMA_CTL_LLP_SRCEN |
+					DMA_CTL_LLP_DSTEN);
+			} else {	/* DMA_TO_DEVICE */
+				lli[idx].sar = cpu_to_le32(addr);
+				lli[idx].dar = cpu_to_le32((u32)dmadr_addr);
+
+				lli[idx].ctl.low = cpu_to_le32(
+					DMA_CTL_TTFC(DMA_CTL_TTFC_M2P_PER) |
+					DMA_CTL_SMS(1) |
+					DMA_CTL_DMS(0) |
+					DMA_CTL_SRC_MSIZE(bl) |
+					DMA_CTL_DST_MSIZE(bl) |
+					DMA_CTL_DINC_NOCHANGE |
+					DMA_CTL_SRC_TRWID(2) |
+					DMA_CTL_DST_TRWID(2) |
+					DMA_CTL_INT_EN |
+					DMA_CTL_LLP_SRCEN |
+					DMA_CTL_LLP_DSTEN);
+			}
+#endif
+			dwc_port_vdbg(qc->ap, "%s setting ctl.high len: 0x%08x val: "
+					"0x%08x\n", __func__, len,
+					DMA_CTL_BLK_TS(len / 4));
+
+			/* Program the LLI CTL high register */
+			dma_ts = DMA_CTL_BLK_TS(len / 4);
+			lli[idx].ctl.high = cpu_to_le32(dma_ts);
+
+			/*
+			 *Program the next pointer.  The next pointer must be
+			 * the physical address, not the virtual address.
+			 */
+			next_llp = (dma_lli + ((idx + 1) * sizeof(struct lli)));
+
+			/* The last 2 bits encode the list master select. */
+#if defined(CONFIG_APM821xx)
+			next_llp = DMA_LLP_LMS(next_llp, DMA_LLP_AHBMASTER1);
+#else
+			next_llp = DMA_LLP_LMS(next_llp, DMA_LLP_AHBMASTER2);
+#endif
+
+			lli[idx].llp = cpu_to_le32(next_llp);
+
+			dwc_port_vdbg(qc->ap, "%s: index %d\n", __func__, idx);
+			dwc_port_vdbg(qc->ap, "%s setting ctl.high with val: 0x%08x\n", __func__, lli[idx].ctl.high);
+			dwc_port_vdbg(qc->ap, "%s setting ctl.low with val: 0x%08x\n", __func__, lli[idx].ctl.low);
+			dwc_port_vdbg(qc->ap, "%s setting lli.dar with val: 0x%08x\n", __func__, lli[idx].dar);
+			dwc_port_vdbg(qc->ap, "%s setting lli.sar with val: 0x%08x\n", __func__, lli[idx].sar);
+			dwc_port_vdbg(qc->ap, "%s setting next_llp with val: 0x%08x\n", __func__, lli[idx].llp);
+
+			idx++;
+			sg_len -= len;
+			addr += len;
+		}
+	}
+
+	/*
+	 * The last next ptr has to be zero and the last control low register
+	 * has to have LLP_SRC_EN and LLP_DST_EN (linked list pointer source
+	 * and destination enable) set back to 0 (disabled.)  This is what tells
+	 * the core that this is the last item in the linked list.
+	 */
+	if (likely(idx)) {
+		lli[idx-1].llp = 0x00000000;
+		lli[idx-1].ctl.low &= DMA_CTL_LLP_DISABLE_LE32;
+
+		/* Flush cache to memory */
+		dma_cache_sync(NULL, lli, (sizeof(struct lli) * idx),
+			       DMA_BIDIRECTIONAL);
+	}
+
+	dwc_port_vdbg(qc->ap, "%s: Final index %d\n", __func__, idx-1);
+	dwc_port_vdbg(qc->ap, "%s setting ctl.high with val: 0x%08x\n", __func__, lli[idx-1].ctl.high);
+	dwc_port_vdbg(qc->ap, "%s setting ctl.low with val: 0x%08x\n", __func__, lli[idx-1].ctl.low);
+	dwc_port_vdbg(qc->ap, "%s setting lli.dar with val: 0x%08x\n", __func__, lli[idx-1].dar);
+	dwc_port_vdbg(qc->ap, "%s setting lli.sar with val: 0x%08x\n", __func__, lli[idx-1].sar);
+	dwc_port_vdbg(qc->ap, "%s setting next_llp with val: 0x%08x\n", __func__, lli[idx-1].llp);
+
+	return idx;
+}
+
+/*
+ * Function: dma_dwc_xfer_start
+ * arguments: Channel number
+ * Return : None
+ * Enables the DMA channel
+ */
+static void dma_dwc_xfer_start(int dma_ch)
+{
+	/* Enable the DMA channel */
+	out_le32(&(sata_dma_regs->dma_chan_en.low),
+		 in_le32(&(sata_dma_regs->dma_chan_en.low)) |
+		 DMA_ENABLE_CHAN(dma_ch));
+
+#if defined(CONFIG_SATA_DWC_VDEBUG)
+	printk("DMA CFG = 0x%08x\n"