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authorAnton Altaparmakov <aia21@cantab.net>2005-09-19 09:47:49 +0100
committerAnton Altaparmakov <aia21@cantab.net>2005-09-19 09:47:49 +0100
commit044a500e46742d39d22f1781cfb64ba93b463e39 (patch)
treeb0313211ea7ba26b90c1083ade0e4c9f486b87db /arch/x86_64/kernel/setup.c
parentf6098cf449b81c14a51e48dd22ae47d03126a1de (diff)
parent6c0741fbdee5bd0f8ed13ac287c4ab18e8ba7d83 (diff)
Merge branch 'master' of /home/src/linux-2.6/
Diffstat (limited to 'arch/x86_64/kernel/setup.c')
-rw-r--r--arch/x86_64/kernel/setup.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c
index 351d8d64c2f..238f73e1a83 100644
--- a/arch/x86_64/kernel/setup.c
+++ b/arch/x86_64/kernel/setup.c
@@ -831,11 +831,26 @@ static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
#endif
}
+#define HWCR 0xc0010015
+
static int __init init_amd(struct cpuinfo_x86 *c)
{
int r;
int level;
+#ifdef CONFIG_SMP
+ unsigned long value;
+
+ // Disable TLB flush filter by setting HWCR.FFDIS:
+ // bit 6 of msr C001_0015
+ //
+ // Errata 63 for SH-B3 steppings
+ // Errata 122 for all(?) steppings
+ rdmsrl(HWCR, value);
+ value |= 1 << 6;
+ wrmsrl(HWCR, value);
+#endif
+
/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
clear_bit(0*32+31, &c->x86_capability);