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author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-10-14 14:39:05 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-10-14 14:39:05 -0700 |
commit | a5ef3f7dcba17e79c21afec38188c4c6a0baf995 (patch) | |
tree | 1961e2e8c2d30dd7a21b93fa7e70dc62f892651d /arch/mips/include/uapi/asm/swab.h | |
parent | d25282d1c9b9bc4cda7f9d3c0205108e99aa7a9d (diff) | |
parent | 35bafbee4b4732a2820bbd0ef141c8192ff29731 (diff) |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS update from Ralf Baechle:
"Cleanups and fixes for breakage that occured earlier during this merge
phase. Also a few patches that didn't make the first pull request.
Of those is the Alchemy work that merges code for many of the SOCs and
evaluation boards thus among other code shrinkage, reduces the number
of MIPS defconfigs by 5."
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (22 commits)
MIPS: SNI: Switch RM400 serial to SCCNXP driver
MIPS: Remove unused empty_bad_pmd_table[] declaration.
MIPS: MT: Remove kspd.
MIPS: Malta: Fix section mismatch.
MIPS: asm-offset.c: Delete unused irq_cpustat_t struct offsets.
MIPS: Alchemy: Merge PB1100/1500 support into DB1000 code.
MIPS: Alchemy: merge PB1550 support into DB1550 code
MIPS: Alchemy: Single kernel for DB1200/1300/1550
MIPS: Optimize TLB refill for RI/XI configurations.
MIPS: proc: Cleanup printing of ASEs.
MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.
MIPS: Add detection of DSP ASE Revision 2.
MIPS: Optimize pgd_init and pmd_init
MIPS: perf: Add perf functionality for BMIPS5000
MIPS: perf: Split the Kconfig option CONFIG_MIPS_MT_SMP
MIPS: perf: Remove unnecessary #ifdef
MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt)
MIPS: perf: Change the "mips_perf_event" table unsupported indicator.
MIPS: Align swapper_pg_dir to 64K for better TLB Refill code.
vmlinux.lds.h: Allow architectures to add sections to the front of .bss
...
Diffstat (limited to 'arch/mips/include/uapi/asm/swab.h')
-rw-r--r-- | arch/mips/include/uapi/asm/swab.h | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/arch/mips/include/uapi/asm/swab.h b/arch/mips/include/uapi/asm/swab.h new file mode 100644 index 00000000000..97c2f81b4b4 --- /dev/null +++ b/arch/mips/include/uapi/asm/swab.h @@ -0,0 +1,59 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 99, 2003 by Ralf Baechle + */ +#ifndef _ASM_SWAB_H +#define _ASM_SWAB_H + +#include <linux/compiler.h> +#include <linux/types.h> + +#define __SWAB_64_THRU_32__ + +#ifdef CONFIG_CPU_MIPSR2 + +static inline __attribute_const__ __u16 __arch_swab16(__u16 x) +{ + __asm__( + " wsbh %0, %1 \n" + : "=r" (x) + : "r" (x)); + + return x; +} +#define __arch_swab16 __arch_swab16 + +static inline __attribute_const__ __u32 __arch_swab32(__u32 x) +{ + __asm__( + " wsbh %0, %1 \n" + " rotr %0, %0, 16 \n" + : "=r" (x) + : "r" (x)); + + return x; +} +#define __arch_swab32 __arch_swab32 + +/* + * Having already checked for CONFIG_CPU_MIPSR2, enable the + * optimized version for 64-bit kernel on r2 CPUs. + */ +#ifdef CONFIG_64BIT +static inline __attribute_const__ __u64 __arch_swab64(__u64 x) +{ + __asm__( + " dsbh %0, %1\n" + " dshd %0, %0" + : "=r" (x) + : "r" (x)); + + return x; +} +#define __arch_swab64 __arch_swab64 +#endif /* CONFIG_64BIT */ +#endif /* CONFIG_CPU_MIPSR2 */ +#endif /* _ASM_SWAB_H */ |