diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2011-10-20 14:59:19 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2011-10-20 14:59:19 +0200 |
| commit | 2f540738f8d228016c6cd0d3b303896c174ecee3 (patch) | |
| tree | 7e6574c041ac4386763f94d3d401d70f4ab6f55b /arch/arm/mach-tegra/timer.c | |
| parent | a3849a4c038a21075a0bc7eaf37f65a93976d10c (diff) | |
| parent | d8e9c00e38f6947cef7f5466a0a3d369461ab97f (diff) | |
Merge branch 'tegra/cleanup' into next/cleanup
Diffstat (limited to 'arch/arm/mach-tegra/timer.c')
| -rw-r--r-- | arch/arm/mach-tegra/timer.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index 90350420c4e..e2272d263a8 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c @@ -62,9 +62,9 @@ static struct timespec persistent_ts; static u64 persistent_ms, last_persistent_ms; #define timer_writel(value, reg) \ - __raw_writel(value, (u32)timer_reg_base + (reg)) + __raw_writel(value, timer_reg_base + (reg)) #define timer_readl(reg) \ - __raw_readl((u32)timer_reg_base + (reg)) + __raw_readl(timer_reg_base + (reg)) static int tegra_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) @@ -133,7 +133,7 @@ static void notrace tegra_update_sched_clock(void) * tegra_rtc driver could be executing to avoid race conditions * on the RTC shadow register */ -u64 tegra_rtc_read_ms(void) +static u64 tegra_rtc_read_ms(void) { u32 ms = readl(rtc_base + RTC_MILLISECONDS); u32 s = readl(rtc_base + RTC_SHADOW_SECONDS); |