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authorAndrew Lunn <andrew@lunn.ch>2014-02-22 20:14:52 +0100
committerJason Cooper <jason@lakedaemon.net>2014-02-22 20:43:49 +0000
commit4b8f7a11c9fb680895e5079788653a59d6bdde16 (patch)
treed20f78bd55eb043f8f9e1be5e702301263b73079 /arch/arm/mach-kirkwood
parent3c317d00ba4a9489c161857a574432c61fde4a2a (diff)
ARM: MM: Add DT binding for Feroceon L2 cache
Instantiate the L2 cache from DT. Indicate in DT where the cache control register is so that it is possible to enable/disable write through on the CPU. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/mach-kirkwood')
-rw-r--r--arch/arm/mach-kirkwood/board-dt.c18
1 files changed, 3 insertions, 15 deletions
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 29c246858d5..ec0702c02d6 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -42,19 +42,6 @@ static void __init kirkwood_map_io(void)
iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
}
-static void __init kirkwood_l2_init(void)
-{
-#ifdef CONFIG_CACHE_FEROCEON_L2
-#ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
- writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
- feroceon_l2_init(1);
-#else
- writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
- feroceon_l2_init(0);
-#endif
-#endif
-}
-
static struct resource kirkwood_cpufreq_resources[] = {
[0] = {
.start = CPU_CONTROL_PHYS,
@@ -211,8 +198,9 @@ static void __init kirkwood_dt_init(void)
BUG_ON(mvebu_mbus_dt_init());
- kirkwood_l2_init();
-
+#ifdef CONFIG_CACHE_FEROCEON_L2
+ feroceon_of_init();
+#endif
kirkwood_cpufreq_init();
kirkwood_cpuidle_init();