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authorLinus Walleij <linus.walleij@linaro.org>2013-09-10 14:10:13 +0200
committerLinus Walleij <linus.walleij@linaro.org>2013-09-27 14:15:44 +0200
commit098e30f6558f8950ed851e874d08bab91c9d4be7 (patch)
treebcdc2bb22b1d50b0371e04a0c814c626f227bc16 /arch/arm/mach-ixp4xx/common.c
parent81ded3c11eeb167c38406247914533872a82db8c (diff)
ARM: ixp4xx: stop broadcasting the custom GPIO API
Now that these custom GPIO accessors are only used from the gpio chip in this machine, move the code out of the include file and right next to the gpiochip implementation. Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Krzysztof Halasa <khc@pm.waw.pl> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/mach-ixp4xx/common.c')
-rw-r--r--arch/arm/mach-ixp4xx/common.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 8708ac8f361..9edaf4734fa 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -81,6 +81,44 @@ void __init ixp4xx_map_io(void)
iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
}
+/*
+ * GPIO-functions
+ */
+/*
+ * The following converted to the real HW bits the gpio_line_config
+ */
+/* GPIO pin types */
+#define IXP4XX_GPIO_OUT 0x1
+#define IXP4XX_GPIO_IN 0x2
+
+/* GPIO signal types */
+#define IXP4XX_GPIO_LOW 0
+#define IXP4XX_GPIO_HIGH 1
+
+/* GPIO Clocks */
+#define IXP4XX_GPIO_CLK_0 14
+#define IXP4XX_GPIO_CLK_1 15
+
+static void gpio_line_config(u8 line, u32 direction)
+{
+ if (direction == IXP4XX_GPIO_IN)
+ *IXP4XX_GPIO_GPOER |= (1 << line);
+ else
+ *IXP4XX_GPIO_GPOER &= ~(1 << line);
+}
+
+static void gpio_line_get(u8 line, int *value)
+{
+ *value = (*IXP4XX_GPIO_GPINR >> line) & 0x1;
+}
+
+static void gpio_line_set(u8 line, int value)
+{
+ if (value == IXP4XX_GPIO_HIGH)
+ *IXP4XX_GPIO_GPOUTR |= (1 << line);
+ else if (value == IXP4XX_GPIO_LOW)
+ *IXP4XX_GPIO_GPOUTR &= ~(1 << line);
+}
/*************************************************************************
* IXP4xx chipset IRQ handling