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| author | Arnd Bergmann <arnd@arndb.de> | 2011-10-07 23:07:41 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2011-10-07 23:07:41 +0200 |
| commit | 8efc59ad6764ade520012cb192cd484e5191cd9c (patch) | |
| tree | d2465d91ebb2652e35cd08f715fc202b3f9e042a /arch/arm/mach-exynos4/clock.c | |
| parent | 6f6184a9d01880a3e21349544f73b3720ce5e152 (diff) | |
| parent | 492c4a0df11573e141a2decc6012b3bddd14a11e (diff) | |
Merge branch 'sirf/cleanup' into next/cleanup
Diffstat (limited to 'arch/arm/mach-exynos4/clock.c')
| -rw-r--r-- | arch/arm/mach-exynos4/clock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index 1561b036a9b..79d6cd0c8e7 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c @@ -1160,7 +1160,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void) vpllsrc = clk_get_rate(&clk_vpllsrc.clk); vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), - __raw_readl(S5P_VPLL_CON1), pll_4650); + __raw_readl(S5P_VPLL_CON1), pll_4650c); clk_fout_apll.ops = &exynos4_fout_apll_ops; clk_fout_mpll.rate = mpll; |