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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-03-18 16:59:10 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-03-18 16:59:10 -0700 |
| commit | c3a0bd7515c682f4529a35318b6712c9ae456edc (patch) | |
| tree | 0dea8aa7f0f1e5f37c4c67faaf3aeb18f4a04701 /arch/arm/kernel/perf_event.c | |
| parent | a41842f70d6d6b0cfde3d21e163add81c4318ebd (diff) | |
| parent | 0d5e6f7ae8609b944c08e8a2f63f7d169c548134 (diff) | |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (23 commits)
ARM: Fix RiscPC decompressor build errors
ARM: Fix sorting of platform group config options and includes
ARM: 5991/1: Fix regression in restore_user_regs macro
ARM: 5989/1: ARM: KGDB: add support for SMP platforms
ARM: 5990/1: ARM: use __armv5tej_mmu_cache_flush for V5TEJ instead of __armv4_mmu_cache_flush
ARM: Add final piece to fix XIP decompressor in read-only memory
video: enable sh_mobile_lcdc on SH-Mobile ARM
ARM: mach-shmobile: ap4evb SDHI0 platform data V2
ARM: mach-shmobile: sh7372 SDHI vector merge
ARM: mach-shmobile: sh7377 SDHI vector merge
ARM: mach-shmobile: sh7367 SDHI vector merge
ARM: mach-shmobile: G4EVM KEYSC platform data
mtd: enable sh_flctl on SH-Mobile ARM
ARM: mach-shmobile: G3EVM FLCTL platform data
ARM: mach-shmobile: G3EVM KEYSC platform data
Video: ARM CLCD: Better fix for swapped IENB and CNTL registers
ARM: Add L2 cache handling to smp boot support
ARM: 5960/1: ARM: perf-events: fix v7 event selection mask
ARM: 5959/1: ARM: perf-events: request PMU interrupts with IRQF_NOBALANCING
ARM: 5988/1: pgprot_dmacoherent() for non-mmu builds
...
Diffstat (limited to 'arch/arm/kernel/perf_event.c')
| -rw-r--r-- | arch/arm/kernel/perf_event.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 3875d99cc40..9e70f2053f9 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -332,7 +332,8 @@ armpmu_reserve_hardware(void) for (i = 0; i < pmu_irqs->num_irqs; ++i) { err = request_irq(pmu_irqs->irqs[i], armpmu->handle_irq, - IRQF_DISABLED, "armpmu", NULL); + IRQF_DISABLED | IRQF_NOBALANCING, + "armpmu", NULL); if (err) { pr_warning("unable to request IRQ%d for ARM " "perf counters\n", pmu_irqs->irqs[i]); @@ -1624,7 +1625,7 @@ enum armv7_counters { /* * EVTSEL: Event selection reg */ -#define ARMV7_EVTSEL_MASK 0x7f /* Mask for writable bits */ +#define ARMV7_EVTSEL_MASK 0xff /* Mask for writable bits */ /* * SELECT: Counter selection reg |