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authorH. Peter Anvin <hpa@linux.intel.com>2013-01-25 16:31:21 -0800
committerH. Peter Anvin <hpa@linux.intel.com>2013-01-25 16:31:21 -0800
commit7b5c4a65cc27f017c170b025f8d6d75dabb11c6f (patch)
tree05deacbc66a9f5c27147a6ea975211ae82281044 /arch/arm/boot/dts/armada-xp.dtsi
parent3596f5bb0a6afd01a784bfe120f420edbbf82861 (diff)
parent949db153b6466c6f7cad5a427ecea94985927311 (diff)
Merge tag 'v3.8-rc5' into x86/mm
The __pa() fixup series that follows touches KVM code that is not present in the existing branch based on v3.7-rc5, so merge in the current upstream from Linus. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/arm/boot/dts/armada-xp.dtsi')
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi89
1 files changed, 86 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 71d6b5d0daf..2e37ef101c9 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,24 +22,39 @@
model = "Marvell Armada XP family SoC";
compatible = "marvell,armadaxp", "marvell,armada-370-xp";
+ L2: l2-cache {
+ compatible = "marvell,aurora-system-cache";
+ reg = <0xd0008000 0x1000>;
+ cache-id-part = <0x100>;
+ wt-override;
+ };
+
mpic: interrupt-controller@d0020000 {
reg = <0xd0020a00 0x1d0>,
- <0xd0021870 0x58>;
+ <0xd0021070 0x58>;
+ };
+
+ armada-370-xp-pmsu@d0022000 {
+ compatible = "marvell,armada-370-xp-pmsu";
+ reg = <0xd0022100 0x430>,
+ <0xd0020800 0x20>;
};
soc {
serial@d0012200 {
- compatible = "ns16550";
+ compatible = "snps,dw-apb-uart";
reg = <0xd0012200 0x100>;
reg-shift = <2>;
interrupts = <43>;
+ reg-io-width = <4>;
status = "disabled";
};
serial@d0012300 {
- compatible = "ns16550";
+ compatible = "snps,dw-apb-uart";
reg = <0xd0012300 0x100>;
reg-shift = <2>;
interrupts = <44>;
+ reg-io-width = <4>;
status = "disabled";
};
@@ -47,9 +62,77 @@
marvell,timer-25Mhz;
};
+ coreclk: mvebu-sar@d0018230 {
+ compatible = "marvell,armada-xp-core-clock";
+ reg = <0xd0018230 0x08>;
+ #clock-cells = <1>;
+ };
+
+ cpuclk: clock-complex@d0018700 {
+ #clock-cells = <1>;
+ compatible = "marvell,armada-xp-cpu-clock";
+ reg = <0xd0018700 0xA0>;
+ clocks = <&coreclk 1>;
+ };
+
+ gateclk: clock-gating-control@d0018220 {
+ compatible = "marvell,armada-xp-gating-clock";
+ reg = <0xd0018220 0x4>;
+ clocks = <&coreclk 0>;
+ #clock-cells = <1>;
+ };
+
system-controller@d0018200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0xd0018200 0x500>;
};
+
+ ethernet@d0030000 {
+ compatible = "marvell,armada-370-neta";
+ reg = <0xd0030000 0x2500>;
+ interrupts = <12>;
+ clocks = <&gateclk 2>;
+ status = "disabled";
+ };
+
+ xor@d0060900 {
+ compatible = "marvell,orion-xor";
+ reg = <0xd0060900 0x100
+ 0xd0060b00 0x100>;
+ clocks = <&gateclk 22>;
+ status = "okay";
+
+ xor10 {
+ interrupts = <51>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor11 {
+ interrupts = <52>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
+ };
+
+ xor@d00f0900 {
+ compatible = "marvell,orion-xor";
+ reg = <0xd00F0900 0x100
+ 0xd00F0B00 0x100>;
+ clocks = <&gateclk 28>;
+ status = "okay";
+
+ xor00 {
+ interrupts = <94>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor01 {
+ interrupts = <95>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
+ };
};
};