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authorDaniel Vetter <daniel.vetter@ffwll.ch>2014-04-24 23:54:53 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-05-16 11:58:33 +0200
commitd41f1efb323e99f680650f77c00907904d246bf7 (patch)
treee9db4ffd3ec7652fd3fae05551ee90e135c732f6
parent9ed109a7b445e3f073d8ea72f888ec80c0532465 (diff)
drm/i915/dp: Move port A pll setup to g4x_pre_enable_dp
Only ilk/snb/ivb need the port A pll setup, so move it to the pre_enable hook for those platforms. We can savely do this since on those platforms there's nothing that touches the hardware between the encoder->mode_set and the encoder->pre_enable calls. Also add a comment that port A is ilk+ only. Reviewed-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 79e045af213..3fa56f38f92 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1002,9 +1002,6 @@ static void intel_dp_mode_set(struct intel_encoder *encoder)
} else {
intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
}
-
- if (port == PORT_A && !IS_VALLEYVIEW(dev))
- ironlake_set_pll_cpu_edp(intel_dp);
}
#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
@@ -1905,8 +1902,11 @@ static void g4x_pre_enable_dp(struct intel_encoder *encoder)
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
- if (dport->port == PORT_A)
+ /* Only ilk+ has port A */
+ if (dport->port == PORT_A) {
+ ironlake_set_pll_cpu_edp(intel_dp);
ironlake_edp_pll_on(intel_dp);
+ }
}
static void vlv_pre_enable_dp(struct intel_encoder *encoder)