diff options
| author | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2013-12-19 16:51:03 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2013-12-24 23:01:12 +0900 |
| commit | 91b56ca10a3cf4999bae5f8b8e7e2723bf4b1363 (patch) | |
| tree | c7caff1df3eb3d9b1b64a8ba9e37668ff8040b35 | |
| parent | cded80f869aef94853e056ab9c21e305b0c26138 (diff) | |
ARM: shmobile: r8a7790: Add QSPI module clock in device tree
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| -rw-r--r-- | arch/arm/boot/dts/r8a7790.dtsi | 11 | ||||
| -rw-r--r-- | include/dt-bindings/clock/r8a7790-clock.h | 1 |
2 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 9c9a9920acc..a1791250bf4 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -615,13 +615,16 @@ mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; + clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, + <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_I2C3 - R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 + R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD + R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 + R8A7790_CLK_I2C0 >; - clock-output-names = "rcan1", "rcan0", "i2c3", "i2c2", "i2c1", "i2c0"; + clock-output-names = + "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0"; }; }; }; diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h index bbabb8e8011..859e9be511d 100644 --- a/include/dt-bindings/clock/r8a7790-clock.h +++ b/include/dt-bindings/clock/r8a7790-clock.h @@ -97,6 +97,7 @@ #define R8A7790_CLK_GPIO0 12 #define R8A7790_CLK_RCAN1 15 #define R8A7790_CLK_RCAN0 16 +#define R8A7790_CLK_QSPI_MOD 17 #define R8A7790_CLK_IICDVFS 26 #define R8A7790_CLK_I2C3 28 #define R8A7790_CLK_I2C2 29 |