diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-12-03 15:39:43 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2013-01-10 21:09:31 +0000 |
| commit | 8e9c24a2b2e00368262b974d6ea1ac5310570bbe (patch) | |
| tree | f7ab7ace096b95a12c43f4bfc40c404e8b78a433 | |
| parent | 9931faca02c604c22335f5a935a501bb2ace6e20 (diff) | |
ARM: virt: avoid clobbering lr when forcing svc mode
The safe_svcmode_maskall macro is used to ensure that we are running in
svc mode, causing an exception return from hvc mode if required.
This patch removes the unneeded lr clobber from the macro and operates
entirely on the temporary parameter register instead.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[will: updated comment]
Signed-off-by: Will Deacon <will.deacon@arm.com>
| -rw-r--r-- | arch/arm/include/asm/assembler.h | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index eb87200aa4b..05ee9eebad6 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -246,18 +246,14 @@ * * This macro is intended for forcing the CPU into SVC mode at boot time. * you cannot return to the original mode. - * - * Beware, it also clobers LR. */ .macro safe_svcmode_maskall reg:req #if __LINUX_ARM_ARCH__ >= 6 mrs \reg , cpsr - mov lr , \reg - and lr , lr , #MODE_MASK - cmp lr , #HYP_MODE - orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT + eor \reg, \reg, #HYP_MODE + tst \reg, #MODE_MASK bic \reg , \reg , #MODE_MASK - orr \reg , \reg , #SVC_MODE + orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE THUMB( orr \reg , \reg , #PSR_T_BIT ) bne 1f orr \reg, \reg, #PSR_A_BIT |