sh: clkfwk: Add a helper for rate rounding by divisor ranges.

This adds a new clk_rate_div_range_round() for implementing rate rounding
by divisor ranges. This can be used trivially by clocks that support
arbitrary ranged divisors without the need for rate table construction.

This should only be used by clocks that both have large divisor ranges in
addition to clocks that will never be arbitrarily scaled, as the lack of
a backing frequency table will prevent cpufreq from being able to do much
of anything with them.

Primarily intended for use as a ->recalc helper.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

2 files changed, 24 insertions, 1 deletions

diff --git a/drivers/sh/clk.c b/drivers/sh/clk.c
index 3ac6fa0005b..018be37ef33 100644
--- a/drivers/sh/clk.c
+++ b/drivers/sh/clk.c
@@ -76,7 +76,7 @@ struct clk_rate_round_data;
 struct clk_rate_round_data {
 	unsigned long rate;
 	unsigned int min, max;
-	long (*func)(unsigned int pos, struct clk_rate_round_data *arg);
+	long (*func)(unsigned int, struct clk_rate_round_data *);
 	void *arg;
 };
 
@@ -148,6 +148,26 @@ long clk_rate_table_round(struct clk *clk,
 	return clk_rate_round_helper(&table_round);
 }
 
+static long clk_rate_div_range_iter(unsigned int pos,
+				    struct clk_rate_round_data *rounder)
+{
+	return clk_get_rate(rounder->arg) / pos;
+}
+
+long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
+			      unsigned int div_max, unsigned long rate)
+{
+	struct clk_rate_round_data div_range_round = {
+		.min	= div_min,
+		.max	= div_max,
+		.func	= clk_rate_div_range_iter,
+		.arg	= clk_get_parent(clk),
+		.rate	= rate,
+	};
+
+	return clk_rate_round_helper(&div_range_round);
+}
+
 int clk_rate_table_find(struct clk *clk,
 			struct cpufreq_frequency_table *freq_table,
 			unsigned long rate)
diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h
index 49f6e9b6eda..4dca992f309 100644
--- a/include/linux/sh_clk.h
+++ b/include/linux/sh_clk.h
@@ -119,6 +119,9 @@ int clk_rate_table_find(struct clk *clk,
 			struct cpufreq_frequency_table *freq_table,
 			unsigned long rate);
 
+long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
+			      unsigned int div_max, unsigned long rate);
+
 #define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags)	\
 {									\
 	.parent		= _parent,					\