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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2014-04-02 16:46:25 +0300
committerTony Lindgren <tony@atomide.com>2014-04-18 15:53:33 -0700
commit8c0b4fd89ead67f5aca63abbadc81dd316b6462c (patch)
tree130cc29dce69a8cd14f957340660b9167d7abdaf
parentada76576404330413eaeb864a265ad250af48d8f (diff)
ARM: dts: dra7xx-clocks: Correct mcasp2_ahclkx_mux bit-shift
The correct bit is 24 for AHCLKX. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/boot/dts/dra7xx-clocks.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index e96da9a898a..cfb8fc753f5 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1640,7 +1640,7 @@
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <28>;
+ ti,bit-shift = <24>;
reg = <0x1860>;
};