diff options
| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2013-05-03 17:23:44 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-05-21 12:00:26 +0200 |
| commit | 3e1f72664e0a8a31e9b90c48459deb6642fd52f3 (patch) | |
| tree | cf20d09a07accd98b0e81f94072b9e7fd8c737bb | |
| parent | 85a02deb4ca5a7e1e39e8538b6eb3c7066469720 (diff) | |
drm/i915: MCH_SSKPD is a 64 bit register on Haswell
And the SNB_READ_WM0_LATENCY macro is not valid anymore because we
have the "New WM0" at 63:56, so the "Old WM0" could maybe be zero if
the new one is not zero.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ad1d35526a8..912ab4d8d72 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4633,7 +4633,7 @@ void intel_init_pm(struct drm_device *dev) } dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; } else if (IS_HASWELL(dev)) { - if (SNB_READ_WM0_LATENCY()) { + if (I915_READ64(MCH_SSKPD)) { dev_priv->display.update_wm = haswell_update_wm; dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; } else { |