Staging: rtl8187se: r8185b_init: fixed a lot of checkpatch.pl issues

Fixed numerous coding style issues using checkpatch.pl

Signed-off-by: Tracey Dent <tdent48227@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 716 insertions, 792 deletions

diff --git a/drivers/staging/rtl8187se/r8185b_init.c b/drivers/staging/rtl8187se/r8185b_init.c
index a0ece1fd64a..46000d72f4c 100644
--- a/drivers/staging/rtl8187se/r8185b_init.c
+++ b/drivers/staging/rtl8187se/r8185b_init.c
@@ -2,14 +2,14 @@
 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
 
 Module Name:
- 	r8185b_init.c
+	r8185b_init.c
 
 Abstract:
- 	Hardware Initialization and Hardware IO for RTL8185B
+	Hardware Initialization and Hardware IO for RTL8185B
 
 Major Change History:
-	When        Who      What
-	----------    ---------------   -------------------------------
+	When		Who				What
+	----------	---------------		-------------------------------
 	2006-11-15    Xiong		Created
 
 Notes:
@@ -29,94 +29,94 @@ Notes:
 #include "ieee80211/dot11d.h"
 
 
-//#define CONFIG_RTL8180_IO_MAP
+/* #define CONFIG_RTL8180_IO_MAP */
 
 #define TC_3W_POLL_MAX_TRY_CNT 5
-static u8 MAC_REG_TABLE[][2]={
-                        //PAGA 0:
-                        // 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185()
-                        // 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().
-                        // 0x1F0~0x1F8  set in MacConfig_85BASIC()
-                        {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
-                        {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
-                        {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
-                        {0x94, 0x0F}, {0x95, 0x32},
-                        {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
-                        {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
-                        {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
-                        {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
-                        {0xff, 0x00},
-
-                        //PAGE 1:
-                        // For Flextronics system Logo PCIHCT failure:
-			// 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1
-                        {0x5e, 0x01},
-                        {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
-                        {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
-                        {0x82, 0xFF}, {0x83, 0x03},
-                        {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, //lzm add 080826
-			{0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},//lzm add 080826
-                        {0xe2, 0x00},
-
-
-                        //PAGE 2:
-                        {0x5e, 0x02},
-                        {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
-                        {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
-                        {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
-                        {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
-                        {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
-                        {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
-                        {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
-
-                        //PAGA 0:
-                        {0x5e, 0x00},{0x9f, 0x03}
-                };
-
-
-static u8  ZEBRA_AGC[]={
+static u8 MAC_REG_TABLE[][2] =	{
+                        /*PAGA 0:	*/
+						/* 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185()	*/
+						/* 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().					*/
+						/* 0x1F0~0x1F8  set in MacConfig_85BASIC()												*/
+						{0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
+						{0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
+						{0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
+						{0x94, 0x0F}, {0x95, 0x32},
+						{0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
+						{0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
+						{0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
+						{0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
+						{0xff, 0x00},
+
+						/*PAGE 1:	*/
+						/* For Flextronics system Logo PCIHCT failure:	*/
+				/* 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1	*/
+						{0x5e, 0x01},
+						{0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
+						{0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
+						{0x82, 0xFF}, {0x83, 0x03},
+						{0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, /* lzm add 080826 */
+						{0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},/* lzm add 080826 */
+						{0xe2, 0x00},
+
+
+						/* PAGE 2: */
+						{0x5e, 0x02},
+						{0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
+						{0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
+						{0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
+						{0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
+						{0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
+						{0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
+						{0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
+
+						/* PAGA 0: */
+						{0x5e, 0x00}, {0x9f, 0x03}
+			};
+
+
+static u8  ZEBRA_AGC[]	=	{
 			0,
-			0x7E,0x7E,0x7E,0x7E,0x7D,0x7C,0x7B,0x7A,0x79,0x78,0x77,0x76,0x75,0x74,0x73,0x72,
-			0x71,0x70,0x6F,0x6E,0x6D,0x6C,0x6B,0x6A,0x69,0x68,0x67,0x66,0x65,0x64,0x63,0x62,
-			0x48,0x47,0x46,0x45,0x44,0x29,0x28,0x27,0x26,0x25,0x24,0x23,0x22,0x21,0x08,0x07,
-			0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-			0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x10,0x11,0x12,0x13,0x15,0x16,
-			0x17,0x17,0x18,0x18,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,
-			0x1f,0x1f,0x1f,0x20,0x20,0x20,0x20,0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x24,
-			0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F
+			0x7E, 0x7E, 0x7E, 0x7E, 0x7D, 0x7C, 0x7B, 0x7A, 0x79, 0x78, 0x77, 0x76, 0x75, 0x74, 0x73, 0x72,
+			0x71, 0x70, 0x6F, 0x6E, 0x6D, 0x6C, 0x6B, 0x6A, 0x69, 0x68, 0x67, 0x66, 0x65, 0x64, 0x63, 0x62,
+			0x48, 0x47, 0x46, 0x45, 0x44, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x08, 0x07,
+			0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x15, 0x16,
+			0x17, 0x17, 0x18, 0x18, 0x19, 0x1a, 0x1a, 0x1b, 0x1b, 0x1c, 0x1c, 0x1d, 0x1d, 0x1d, 0x1e, 0x1e,
+			0x1f, 0x1f, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x21, 0x22, 0x22, 0x22, 0x23, 0x23, 0x24,
+			0x24, 0x25, 0x25, 0x25, 0x26, 0x26, 0x27, 0x27, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F
 			};
 
-static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
-			0x0096,0x0076,0x0056,0x0036,0x0016,0x01f6,0x01d6,0x01b6,
-			0x0196,0x0176,0x00F7,0x00D7,0x00B7,0x0097,0x0077,0x0057,
-			0x0037,0x00FB,0x00DB,0x00BB,0x00FF,0x00E3,0x00C3,0x00A3,
-			0x0083,0x0063,0x0043,0x0023,0x0003,0x01E3,0x01C3,0x01A3,
-			0x0183,0x0163,0x0143,0x0123,0x0103
+static u32 ZEBRA_RF_RX_GAIN_TABLE[]	=	{
+			0x0096, 0x0076, 0x0056, 0x0036, 0x0016, 0x01f6, 0x01d6, 0x01b6,
+			0x0196, 0x0176, 0x00F7, 0x00D7, 0x00B7, 0x0097, 0x0077, 0x0057,
+			0x0037, 0x00FB, 0x00DB, 0x00BB, 0x00FF, 0x00E3, 0x00C3, 0x00A3,
+			0x0083, 0x0063, 0x0043, 0x0023, 0x0003, 0x01E3, 0x01C3, 0x01A3,
+			0x0183, 0x0163, 0x0143, 0x0123, 0x0103
 	};
 
-static u8 OFDM_CONFIG[]={
-			// OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX
-			// OFDM reg0x3C[4]=1'b1: Enable RX power saving mode
-			// ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test
+static u8 OFDM_CONFIG[]	=	{
+			/* OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX				*/
+			/* OFDM reg0x3C[4]=1'b1: Enable RX power saving mode					*/
+			/* ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test	*/
 
-			// 0x00
+			/* 0x00	*/
 			0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
 			0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
-			// 0x10
+			/* 0x10	*/
 			0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
 			0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
-			// 0x20
+			/* 0x20	*/
 			0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
 			0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
-			// 0x30
+			/* 0x30	*/
 			0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
 			0xD8, 0x3C, 0x7B, 0x10, 0x10
 		};
 
-/*---------------------------------------------------------------
-  * Hardware IO
-  * the code is ported from Windows source code
-  ----------------------------------------------------------------*/
+/*	---------------------------------------------------------------
+	*	Hardware IO
+	*	the code is ported from Windows source code
+	----------------------------------------------------------------*/
 
 void
 PlatformIOWrite1Byte(
@@ -126,7 +126,7 @@ PlatformIOWrite1Byte(
 	)
 {
 	write_nic_byte(dev, offset, data);
-	read_nic_byte(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
+	read_nic_byte(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko.	*/
 
 }
 
@@ -138,7 +138,7 @@ PlatformIOWrite2Byte(
 	)
 {
 	write_nic_word(dev, offset, data);
-	read_nic_word(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
+	read_nic_word(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
 
 
 }
@@ -151,9 +151,9 @@ PlatformIOWrite4Byte(
 	u32		data
 	)
 {
-//{by amy 080312
-if (offset == PhyAddr)
-	{//For Base Band configuration.
+/* {by amy 080312 */
+if (offset == PhyAddr)	{
+/* For Base Band configuration. */
 		unsigned char	cmdByte;
 		unsigned long	dataBytes;
 		unsigned char	idx;
@@ -162,37 +162,36 @@ if (offset == PhyAddr)
 		cmdByte = (u8)(data & 0x000000ff);
 		dataBytes = data>>8;
 
-		//
-		// 071010, rcnjko:
-		// The critical section is only BB read/write race condition.
-		// Assumption:
-		// 1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
-		// acquiring the spinlock in such context.
-		// 2. PlatformIOWrite4Byte() MUST NOT be recursive.
-		//
-//		NdisAcquireSpinLock( &(pDevice->IoSpinLock) );
-
-		for(idx = 0; idx < 30; idx++)
-		{ // Make sure command bit is clear before access it.
+		/*
+			071010, rcnjko:
+			The critical section is only BB read/write race condition.
+			Assumption:
+			1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
+			acquiring the spinlock in such context.
+			2. PlatformIOWrite4Byte() MUST NOT be recursive.
+		*/
+/*		NdisAcquireSpinLock( &(pDevice->IoSpinLock) );	*/
+
+		for (idx = 0; idx < 30; idx++)	{ 
+		/* Make sure command bit is clear before access it.	*/
 			u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
-			if((u1bTmp & BIT7) == 0)
+			if ((u1bTmp & BIT7) == 0)
 				break;
 			else
 				mdelay(10);
 		}
 
-		for(idx=0; idx < 3; idx++)
-		{
-			PlatformIOWrite1Byte(dev,offset+1+idx,((u8*)&dataBytes)[idx] );
-		}
+		for (idx = 0; idx < 3; idx++)
+			PlatformIOWrite1Byte(dev, offset+1+idx, ((u8 *)&dataBytes)[idx]);
+
 		write_nic_byte(dev, offset, cmdByte);
 
-//		NdisReleaseSpinLock( &(pDevice->IoSpinLock) );
+/*		NdisReleaseSpinLock( &(pDevice->IoSpinLock) ); */
 	}
-//by amy 080312}
-	else{
+/* by amy 080312} */
+	else	{
 		write_nic_dword(dev, offset, data);
-		read_nic_dword(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
+		read_nic_dword(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
 	}
 }
 
@@ -256,59 +255,49 @@ HwHSSIThreeWire(
 	u8	TryCnt;
 	u8	u1bTmp;
 
-	do
-	{
-		// Check if WE and RE are cleared.
-		for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
-		{
+	do	{
+		/* Check if WE and RE are cleared. */
+		for (TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)	{
 			u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
-			if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
-			{
+			if ((u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0)
 				break;
-			}
+
 			udelay(10);
 		}
 		if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 			panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 
-		// RTL8187S HSSI Read/Write Function
+		/* RTL8187S HSSI Read/Write Function */
 		u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 
-		if(bSI)
-		{
-			u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
-		}else
-		{
-			u1bTmp &= ~RF_SW_CFG_SI;  //reg08[1]=0 Parallel Interface(PI)
-		}
+		if (bSI)
+			u1bTmp |=   RF_SW_CFG_SI;   /* reg08[1]=1 Serial Interface(SI)	*/
+
+		else
+			u1bTmp &= ~RF_SW_CFG_SI;  /* reg08[1]=0 Parallel Interface(PI)	*/
+
 
 		write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 
-		if(bSI)
-		{
-			// jong: HW SI read must set reg84[3]=0.
+		if (bSI)	{
+			/* jong: HW SI read must set reg84[3]=0. */
 			u1bTmp = read_nic_byte(dev, RFPinsSelect);
 			u1bTmp &= ~BIT3;
-			write_nic_byte(dev, RFPinsSelect, u1bTmp );
+			write_nic_byte(dev, RFPinsSelect, u1bTmp);
 		}
-	 	// Fill up data buffer for write operation.
-
-		if(bWrite)
-		{
-			if(nDataBufBitCnt == 16)
-			{
-				write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf));
-			}
-			else if(nDataBufBitCnt == 64)  // RTL8187S shouldn't enter this case
-			{
-				write_nic_dword(dev, SW_3W_DB0, *((u32*)pDataBuf));
-				write_nic_dword(dev, SW_3W_DB1, *((u32*)(pDataBuf + 4)));
-			}
-			else
-			{
+		/*  Fill up data buffer for write operation. */
+
+		if (bWrite)	{
+			if (nDataBufBitCnt == 16)	{
+				write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
+			}	else if (nDataBufBitCnt == 64)	{
+			/* RTL8187S shouldn't enter this case */
+				write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf));
+				write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4)));
+			}	else	{
 				int idx;
 				int ByteCnt = nDataBufBitCnt / 8;
-                                //printk("%d\n",nDataBufBitCnt);
+								/* printk("%d\n",nDataBufBitCnt); */
 				if ((nDataBufBitCnt % 8) != 0)
 				panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 				nDataBufBitCnt);
@@ -317,67 +306,53 @@ HwHSSIThreeWire(
 				panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 				nDataBufBitCnt);
 
-				for(idx = 0; idx < ByteCnt; idx++)
-				{
+				for (idx = 0; idx < ByteCnt; idx++)
 					write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
-				}
-			}
-		}
-		else		//read
-		{
-			if(bSI)
-			{
-				// SI - reg274[3:0] : RF register's Address
-				write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf) );
+
 			}
-			else
-			{
-				// PI - reg274[15:12] : RF register's Address
-				write_nic_word(dev, SW_3W_DB0, (*((u16*)pDataBuf)) << 12);
+		}	else	{	/* read */
+			if (bSI)	{
+				/* SI - reg274[3:0] : RF register's Address	*/
+				write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
+			}	else	{
+				/*  PI - reg274[15:12] : RF register's Address */
+				write_nic_word(dev, SW_3W_DB0, (*((u16 *)pDataBuf)) << 12);
 			}
 		}
 
-		// Set up command: WE or RE.
-		if(bWrite)
-		{
+		/* Set up command: WE or RE. */
+		if (bWrite)
 			write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
-		}
+
 		else
-		{
 			write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
-		}
 
-		// Check if DONE is set.
-		for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
-		{
+
+		/* Check if DONE is set. */
+		for (TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)	{
 			u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
-			if(  (u1bTmp & SW_3W_CMD1_DONE) != 0 )
-			{
+			if ((u1bTmp & SW_3W_CMD1_DONE) != 0)
 				break;
-			}
+
 			udelay(10);
 		}
 
 		write_nic_byte(dev, SW_3W_CMD1, 0);
 
-		// Read back data for read operation.
-		if(bWrite == 0)
-		{
-			if(bSI)
-			{
-				//Serial Interface : reg363_362[11:0]
-				*((u16*)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
-			}
-			else
-			{
-				//Parallel Interface : reg361_360[11:0]
-				*((u16*)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
+		/* Read back data for read operation.	*/
+		if (bWrite == 0)	{
+			if (bSI)		{
+				/* Serial Interface : reg363_362[11:0] */
+				*((u16 *)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
+			}	else	{
+				/* Parallel Interface : reg361_360[11:0] */
+				*((u16 *)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
 			}
 
-			*((u16*)pDataBuf) &= 0x0FFF;
+			*((u16 *)pDataBuf) &= 0x0FFF;
 		}
 
-	}while(0);
+	}	while (0);
 
 	return bResult;
 }
@@ -410,25 +385,25 @@ u32 RF_ReadReg(struct net_device *dev, u8 offset)
 }
 
 
-// by Owen on 04/07/14 for writing BB register successfully
+/* by Owen on 04/07/14 for writing BB register successfully */
 void
 WriteBBPortUchar(
 	struct net_device *dev,
 	u32		Data
 	)
 {
-	//u8	TimeoutCounter;
+	/* u8	TimeoutCounter; */
 	u8	RegisterContent;
 	u8	UCharData;
 
 	UCharData = (u8)((Data & 0x0000ff00) >> 8);
 	PlatformIOWrite4Byte(dev, PhyAddr, Data);
-	//for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--)
+	/* for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--) */
 	{
 		PlatformIOWrite4Byte(dev, PhyAddr, Data & 0xffffff7f);
 		RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
-		//if(UCharData == RegisterContent)
-		//	break;
+		/*if(UCharData == RegisterContent)	*/
+		/*	break;	*/
 	}
 }
 
@@ -438,7 +413,7 @@ ReadBBPortUchar(
 	u32		addr
 	)
 {
-	//u8	TimeoutCounter;
+	/*u8	TimeoutCounter; */
 	u8	RegisterContent;
 
 	PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
@@ -446,93 +421,87 @@ ReadBBPortUchar(
 
 	return RegisterContent;
 }
-//{by amy 080312
-//
-//	Description:
-//		Perform Antenna settings with antenna diversity on 87SE.
-//    Created by Roger, 2008.01.25.
-//
+/* {by amy 080312 */
+/*
+	Description:
+	Perform Antenna settings with antenna diversity on 87SE.
+		Created by Roger, 2008.01.25.
+*/
 bool
 SetAntennaConfig87SE(
 	struct net_device *dev,
-	u8			DefaultAnt,		// 0: Main, 1: Aux.
-	bool		bAntDiversity 	// 1:Enable, 0: Disable.
+	u8			DefaultAnt,		/* 0: Main, 1: Aux.			*/
+	bool		bAntDiversity	/* 1:Enable, 0: Disable.	*/
 )
 {
 	struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 	bool   bAntennaSwitched = true;
 
-	//printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity);
+	/* printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity); */
 
-	// Threshold for antenna diversity.
-	write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
+	/* Threshold for antenna diversity.	*/
+	write_phy_cck(dev, 0x0c, 0x09); /* Reg0c : 09 */
 
-	if( bAntDiversity )  //  Enable Antenna Diversity.
-	{
-		if( DefaultAnt == 1 )  // aux antenna
-		{
-			// Mac register, aux antenna
+	if (bAntDiversity)	{	/*	Enable Antenna Diversity.	*/
+		if (DefaultAnt == 1)	{	/* aux antenna			*/
+
+			/* Mac register, aux antenna	*/
 			write_nic_byte(dev, ANTSEL, 0x00);
 
-			// Config CCK RX antenna.
-			write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
-			write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
+			/* Config CCK RX antenna.		*/
+			write_phy_cck(dev, 0x11, 0xbb); /* Reg11 : bb */
+			write_phy_cck(dev, 0x01, 0xc7); /* Reg01 : c7 */
 
-			// Config OFDM RX antenna.
-			write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
-			write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
-		}
-		else //  use main antenna
-		{
-			// Mac register, main antenna
+			/* Config OFDM RX antenna.	*/
+			write_phy_ofdm(dev, 0x0D, 0x54);	/* Reg0d : 54	*/
+			write_phy_ofdm(dev, 0x18, 0xb2);	/* Reg18 : b2		*/
+		}	else	{	/*  use main antenna	*/
+			/* Mac register, main antenna		*/
 			write_nic_byte(dev, ANTSEL, 0x03);
-			//base band
-			// Config CCK RX antenna.
-			write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
-			write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
-
-			// Config OFDM RX antenna.
-			write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
-			write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
+			/* base band				*/
+			/*  Config CCK RX antenna.	*/
+			write_phy_cck(dev, 0x11, 0x9b); /* Reg11 : 9b	*/
+			write_phy_cck(dev, 0x01, 0xc7); /* Reg01 : c7	*/
+
+			/* Config OFDM RX antenna. */
+			write_phy_ofdm(dev, 0x0d, 0x5c);  /* Reg0d : 5c	*/
+			write_phy_ofdm(dev, 0x18, 0xb2);  /* Reg18 : b2	*/
 		}
-	}
-	else   // Disable Antenna Diversity.
-	{
-		if( DefaultAnt == 1 ) // aux Antenna
-		{
-			// Mac register, aux antenna
+	}	else	{
+		/* Disable Antenna Diversity. */
+		if (DefaultAnt == 1)	{	/* aux Antenna */
+			/* Mac register, aux antenna */
 			write_nic_byte(dev, ANTSEL, 0x00);
 
-			// Config CCK RX antenna.
-			write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
-			write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
+			/* Config CCK RX antenna. */
+			write_phy_cck(dev, 0x11, 0xbb); /* Reg11 : bb	*/
+			write_phy_cck(dev, 0x01, 0x47); /* Reg01 : 47	*/
 
-			// Config OFDM RX antenna.
-			write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
-			write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
-		}
-		else // main Antenna
-		{
-			// Mac register, main antenna
+			/* Config OFDM RX antenna. */
+			write_phy_ofdm(dev, 0x0D, 0x54);	/* Reg0d : 54	*/
+			write_phy_ofdm(dev, 0x18, 0x32);	/* Reg18 : 32	*/
+		}	else	{	/* main Antenna */
+			/* Mac register, main antenna */
 			write_nic_byte(dev, ANTSEL, 0x03);
 
-			// Config CCK RX antenna.
-			write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
-			write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
+			/* Config CCK RX antenna.	*/
+			write_phy_cck(dev, 0x11, 0x9b); /* Reg11 : 9b */
+			write_phy_cck(dev, 0x01, 0x47); /* Reg01 : 47 */
 
-			// Config OFDM RX antenna.
-			write_phy_ofdm(dev, 0x0D, 0x5c);   // Reg0d : 5c
-			write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
+			/* Config OFDM RX antenna.		*/
+			write_phy_ofdm(dev, 0x0D, 0x5c);	/* Reg0d : 5c	*/
+			write_phy_ofdm(dev, 0x18, 0x32);	/*Reg18 : 32	*/
 		}
 	}
-	priv->CurrAntennaIndex = DefaultAnt; // Update default settings.
+	priv->CurrAntennaIndex = DefaultAnt; /* Update default settings. */
 	return	bAntennaSwitched;
 }
-//by amy 080312
-/*---------------------------------------------------------------
-  * Hardware Initialization.
-  * the code is ported from Windows source code
-  ----------------------------------------------------------------*/
+/* by amy 080312 */
+/*
+---------------------------------------------------------------
+	*	Hardware Initialization.
+	*	the code is ported from Windows source code
+----------------------------------------------------------------*/
 
 void
 ZEBRA_Config_85BASIC_HardCode(
@@ -542,36 +511,38 @@ ZEBRA_Config_85BASIC_HardCode(
 
 	struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 	u32			i;
-	u32	addr,data;
+	u32	addr, data;
 	u32	u4bRegOffset, u4bRegValue, u4bRF23, u4bRF24;
-       u8			u1b24E;
+	u8			u1b24E;
 	int d_cut = 0;
 
 
-	//=============================================================================
-	// 87S_PCIE :: RADIOCFG.TXT
-	//=============================================================================
+/*
+=============================================================================
+	87S_PCIE :: RADIOCFG.TXT
+=============================================================================
+*/
 
 
-	// Page1 : reg16-reg30
-	RF_WriteReg(dev, 0x00, 0x013f);			mdelay(1); // switch to page1
-	u4bRF23= RF_ReadReg(dev, 0x08);			mdelay(1);
-	u4bRF24= RF_ReadReg(dev, 0x09);			mdelay(1);
+	/* Page1 : reg16-reg30 */
+	RF_WriteReg(dev, 0x00, 0x013f);			mdelay(1); /* switch to page1 */
+	u4bRF23 = RF_ReadReg(dev, 0x08);			mdelay(1);
+	u4bRF24 = RF_ReadReg(dev, 0x09);			mdelay(1);
 
 	if (u4bRF23 == 0x818 && u4bRF24 == 0x70C) {
 		d_cut = 1;
 		printk(KERN_INFO "rtl8187se: card type changed from C- to D-cut\n");
 	}
 
-	// Page0 : reg0-reg15
+	/* Page0 : reg0-reg15	*/
 
-	RF_WriteReg(dev, 0x00, 0x009f);      	mdelay(1);// 1
+	RF_WriteReg(dev, 0x00, 0x009f);			mdelay(1);/* 1	*/
 
 	RF_WriteReg(dev, 0x01, 0x06e0);			mdelay(1);
 
-	RF_WriteReg(dev, 0x02, 0x004d);			mdelay(1);// 2
+	RF_WriteReg(dev, 0x02, 0x004d);			mdelay(1);/* 2	*/
 
-	RF_WriteReg(dev, 0x03, 0x07f1);			mdelay(1);// 3
+	RF_WriteReg(dev, 0x03, 0x07f1);			mdelay(1);/* 3	*/
 
 	RF_WriteReg(dev, 0x04, 0x0975);			mdelay(1);
 	RF_WriteReg(dev, 0x05, 0x0c72);			mdelay(1);
@@ -587,7 +558,7 @@ ZEBRA_Config_85BASIC_HardCode(
 	RF_WriteReg(dev, 0x0f, 0x0990);			mdelay(1);
 
 
-	// Page1 : reg16-reg30
+	/*  Page1 : reg16-reg30 */
 	RF_WriteReg(dev, 0x00, 0x013f);			mdelay(1);
 
 	RF_WriteReg(dev, 0x03, 0x0806);			mdelay(1);
@@ -598,143 +569,142 @@ ZEBRA_Config_85BASIC_HardCode(
 
 
 	RF_WriteReg(dev, 0x07, 0x01A0);			mdelay(1);
-// Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl.
+/* Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl. */
 	RF_WriteReg(dev, 0x0a, 0x0001);			mdelay(1);
 	RF_WriteReg(dev, 0x0b, 0x0418);			mdelay(1);
 
 	if (d_cut) {
 		RF_WriteReg(dev, 0x0c, 0x0fbe);			mdelay(1);
 		RF_WriteReg(dev, 0x0d, 0x0008);			mdelay(1);
-		RF_WriteReg(dev, 0x0e, 0x0807);			mdelay(1); // RX LO buffer
-	} else {
+		RF_WriteReg(dev, 0x0e, 0x0807);			mdelay(1); /* RX LO buffer */
+	}	else	{
 		RF_WriteReg(dev, 0x0c, 0x0fbe);			mdelay(1);
 		RF_WriteReg(dev, 0x0d, 0x0008);			mdelay(1);
-		RF_WriteReg(dev, 0x0e, 0x0806);			mdelay(1); // RX LO buffer
+		RF_WriteReg(dev, 0x0e, 0x0806);			mdelay(1); /* RX LO buffer */
 	}
 
 	RF_WriteReg(dev, 0x0f, 0x0acc);			mdelay(1);
 
-	RF_WriteReg(dev, 0x00, 0x01d7);			mdelay(1);// 6
+	RF_WriteReg(dev, 0x00, 0x01d7);			mdelay(1); /* 6 */
 
 	RF_WriteReg(dev, 0x03, 0x0e00);			mdelay(1);
 	RF_WriteReg(dev, 0x04, 0x0e50);			mdelay(1);
-	for(i=0;i<=36;i++)
-	{
+	for (i = 0; i <= 36; i++)	{
 		RF_WriteReg(dev, 0x01, i);                     mdelay(1);
 		RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
 	}
 
-	RF_WriteReg(dev, 0x05, 0x0203);			mdelay(1); 	/// 203, 343
-	RF_WriteReg(dev, 0x06, 0x0200);			mdelay(1);	// 400
+	RF_WriteReg(dev, 0x05, 0x0203);			mdelay(1);	/* 203, 343	*/
+	RF_WriteReg(dev, 0x06, 0x0200);			mdelay(1);	/* 400		*/
 
-	RF_WriteReg(dev, 0x00, 0x0137);			mdelay(1);	// switch to reg16-reg30, and HSSI disable 137
-	mdelay(10); 	// Deay 10 ms. //0xfd
+	RF_WriteReg(dev, 0x00, 0x0137);			mdelay(1);	/* switch to reg16-reg30, and HSSI disable 137	*/
+	mdelay(10);		/* Deay 10 ms.	*/	/* 0xfd */
 
-	RF_WriteReg(dev, 0x0d, 0x0008);			mdelay(1);	// Z4 synthesizer loop filter setting, 392
-	mdelay(10); 	// Deay 10 ms. //0xfd
+	RF_WriteReg(dev, 0x0d, 0x0008);			mdelay(1);	/* Z4 synthesizer loop filter setting, 392		*/
+	mdelay(10);		/* Deay 10 ms.	*/	/* 0xfd */
 
-	RF_WriteReg(dev, 0x00, 0x0037);			mdelay(1);	// switch to reg0-reg15, and HSSI disable
-	mdelay(10); 	// Deay 10 ms. //0xfd
+	RF_WriteReg(dev, 0x00, 0x0037);			mdelay(1);	/* switch to reg0-reg15, and HSSI disable		*/
+	mdelay(10);		/* Deay 10 ms.	*/	/* 0xfd	*/
 
-	RF_WriteReg(dev, 0x04, 0x0160);			mdelay(1); 	// CBC on, Tx Rx disable, High gain
-	mdelay(10); 	// Deay 10 ms. //0xfd
+	RF_WriteReg(dev, 0x04, 0x0160);			mdelay(1);	/* CBC on, Tx Rx disable, High gain				*/
+	mdelay(10);		/* Deay 10 ms.	*/	/* 0xfd	*/
 
-	RF_WriteReg(dev, 0x07, 0x0080);			mdelay(1);	// Z4 setted channel 1
-	mdelay(10); 	// Deay 10 ms. //0xfd
+	RF_WriteReg(dev, 0x07, 0x0080);			mdelay(1);	/* Z4 setted channel 1							*/
+	mdelay(10);		/* Deay 10 ms.	*/	/* 0xfd	*/
 
-	RF_WriteReg(dev, 0x02, 0x088D);			mdelay(1);	// LC calibration
-	mdelay(200); 	// Deay 200 ms. //0xfd
-	mdelay(10); 	// Deay 10 ms. //0xfd
-	mdelay(10); 	// Deay 10 ms. //0xfd
+	RF_WriteReg(dev, 0x02, 0x088D);			mdelay(1);	/* LC calibration								*/
+	mdelay(200);	/* Deay 200 ms.	*/	/* 0xfd	*/
+	mdelay(10);		/* Deay 10 ms.	*/	/* 0xfd	*/
+	mdelay(10);		/* Deay 10 ms.	*/	/* 0xfd	*/
 
-	RF_WriteReg(dev, 0x00, 0x0137);			mdelay(1);	// switch to reg16-reg30 137, and HSSI disable 137
-	mdelay(10); 	// Deay 10 ms. //0xfd
+	RF_WriteReg(dev, 0x00, 0x0137);			mdelay(1);	/* switch to reg16-reg30 137, and HSSI disable 137	*/
+	mdelay(10);		/* Deay 10 ms.	*/	/* 0xfd	*/
 
 	RF_WriteReg(dev, 0x07, 0x0000);			mdelay(1);
 	RF_WriteReg(dev, 0x07, 0x0180);			mdelay(1);
 	RF_WriteReg(dev, 0x07, 0x0220);			mdelay(1);
 	RF_WriteReg(dev, 0x07, 0x03E0);			mdelay(1);
 
-	// DAC calibration off 20070702
+	/* DAC calibration off 20070702	*/
 	RF_WriteReg(dev, 0x06, 0x00c1);			mdelay(1);
 	RF_WriteReg(dev, 0x0a, 0x0001);			mdelay(1);
-//{by amy 080312
-	// For crystal calibration, added by Roger, 2007.12.11.
-	if( priv->bXtalCalibration ) // reg 30.
-	{ // enable crystal calibration.
-		// RF Reg[30], (1)Xin:[12:9], Xout:[8:5],  addr[4:0].
-		// (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
-		// (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
-		// So we should minus 4 BITs offset.
-		RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5)|(priv->XtalCal_Xout<<1)|BIT11|BIT9);			mdelay(1);
+/* {by amy 080312 */
+	/* For crystal calibration, added by Roger, 2007.12.11. */
+	if (priv->bXtalCalibration)	{	/* reg 30.	*/
+	 /* enable crystal calibration.
+			RF Reg[30], (1)Xin:[12:9], Xout:[8:5],  addr[4:0].
+			(2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
+			(3)RF signal on/off when calibration[13], default: on, set BIT13=0.
+			So we should minus 4 BITs offset.		*/
+		RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11 | BIT9);			mdelay(1);
 		printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
-				(priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11| BIT9);
-	}
-	else
-	{ // using default value. Xin=6, Xout=6.
+				(priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11 | BIT9);
+	}	else	{
+		/* using default value. Xin=6, Xout=6.	*/
 		RF_WriteReg(dev, 0x0f, 0x0acc);			mdelay(1);
 	}
-//by amy 080312
-
-	RF_WriteReg(dev, 0x00, 0x00bf);			mdelay(1); // switch to reg0-reg15, and HSSI enable
-	RF_WriteReg(dev, 0x0d, 0x08df);			mdelay(1); // Rx BB start calibration, 00c//+edward
-	RF_WriteReg(dev, 0x02, 0x004d);			mdelay(1); // temperature meter off
-	RF_WriteReg(dev, 0x04, 0x0975);			mdelay(1); // Rx mode
-	mdelay(10);	// Deay 10 ms. //0xfe
-	mdelay(10);	// Deay 10 ms. //0xfe
-	mdelay(10);	// Deay 10 ms. //0xfe
-	RF_WriteReg(dev, 0x00, 0x0197);			mdelay(1); // Rx mode//+edward
-	RF_WriteReg(dev, 0x05, 0x05ab);			mdelay(1); // Rx mode//+edward
-	RF_WriteReg(dev, 0x00, 0x009f);			mdelay(1); // Rx mode//+edward
-
-	RF_WriteReg(dev, 0x01, 0x0000);			mdelay(1); // Rx mode//+edward
-	RF_WriteReg(dev, 0x02, 0x0000);			mdelay(1); // Rx mode//+edward
-	//power save parameters.
+/* by amy 080312 */
+
+	RF_WriteReg(dev, 0x00, 0x00bf);			mdelay(1); /* switch to reg0-reg15, and HSSI enable	*/
+	RF_WriteReg(dev, 0x0d, 0x08df);			mdelay(1); /* Rx BB start calibration, 00c//+edward	*/
+	RF_WriteReg(dev, 0x02, 0x004d);			mdelay(1); /* temperature meter off					*/
+	RF_WriteReg(dev, 0x04, 0x0975);			mdelay(1); /* Rx mode								*/
+	mdelay(10);	/* Deay 10 ms.*/	/* 0xfe	*/
+	mdelay(10);	/* Deay 10 ms.*/	/* 0xfe	*/
+	mdelay(10);	/* Deay 10 ms.*/	/* 0xfe	*/
+	RF_WriteReg(dev, 0x00, 0x0197);			mdelay(1); /* Rx mode*/	/*+edward	*/
+	RF_WriteReg(dev, 0x05, 0x05ab);			mdelay(1); /* Rx mode*/	/*+edward	*/
+	RF_WriteReg(dev, 0x00, 0x009f);			mdelay(1); /* Rx mode*/	/*+edward	*/
+
+	RF_WriteReg(dev, 0x01, 0x0000);			mdelay(1); /* Rx mode*/	/*+edward	*/
+	RF_WriteReg(dev, 0x02, 0x0000);			mdelay(1); /* Rx mode*/	/*+edward	*/
+	/* power save parameters.	*/
 	u1b24E = read_nic_byte(dev, 0x24E);
 	write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
 
-	//=============================================================================
-
-	//=============================================================================
-	// CCKCONF.TXT
-	//=============================================================================
+	/*=============================================================================
 
+	=============================================================================
+	CCKCONF.TXT
+	=============================================================================
+	*/
 	/*	[POWER SAVE] Power Saving Parameters by jong. 2007-11-27
-	   	CCK reg0x00[7]=1'b1 :power saving for TX (default)
+		CCK reg0x00[7]=1'b1 :power saving for TX (default)
 		CCK reg0x00[6]=1'b1: power saving for RX (default)
 		CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
 		CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
 		CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
 	*/
 
-	write_phy_cck(dev,0x00,0xc8);
-	write_phy_cck(dev,0x06,0x1c);
-	write_phy_cck(dev,0x10,0x78);
-	write_phy_cck(dev,0x2e,0xd0);
-	write_phy_cck(dev,0x2f,0x06);
-	write_phy_cck(dev,0x01,0x46);
+	write_phy_cck(dev, 0x00, 0xc8);
+	write_phy_cck(dev, 0x06, 0x1c);
+	write_phy_cck(dev, 0x10, 0x78);
+	write_phy_cck(dev, 0x2e, 0xd0);
+	write_phy_cck(dev, 0x2f, 0x06);
+	write_phy_cck(dev, 0x01, 0x46);
 
-	// power control
+	/* power control	*/
 	write_nic_byte(dev, CCK_TXAGC, 0x10);
 	write_nic_byte(dev, OFDM_TXAGC, 0x1B);
 	write_nic_byte(dev, ANTSEL, 0x03);
 
 
 
-	//=============================================================================
-	// AGC.txt
-	//=============================================================================
+	/*
+	=============================================================================
+		AGC.txt
+	=============================================================================
+	*/
 
 	write_phy_ofdm(dev, 0x00, 0x12);
 
-	for (i=0; i<128; i++)
-	{
+	for (i = 0; i < 128; i++)	{
 
 		data = ZEBRA_AGC[i+1];
 		data = data << 8;
 		data = data | 0x0000008F;
 
-		addr = i + 0x80; //enable writing AGC table
+		addr = i + 0x80; /* enable writing AGC table */
 		addr = addr << 8;
 		addr = addr | 0x0000008E;
 
@@ -743,18 +713,19 @@ ZEBRA_Config_85BASIC_HardCode(
 		WriteBBPortUchar(dev, 0x0000008E);
 	}
 
-	PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080);	// Annie, 2006-05-05
+	PlatformIOWrite4Byte(dev, PhyAddr, 0x00001080);	/* Annie, 2006-05-05 */
 
-	//=============================================================================
+	/*
+	=============================================================================
 
-	//=============================================================================
-	// OFDMCONF.TXT
-	//=============================================================================
+	=============================================================================
+	OFDMCONF.TXT
+	=============================================================================
+	*/
 
-	for(i=0; i<60; i++)
-	{
-		u4bRegOffset=i;
-		u4bRegValue=OFDM_CONFIG[i];
+	for (i = 0; i < 60; i++)	{
+		u4bRegOffset = i;
+		u4bRegValue = OFDM_CONFIG[i];
 
 		WriteBBPortUchar(dev,
 						(0x00000080 |
@@ -762,14 +733,16 @@ ZEBRA_Config_85BASIC_HardCode(
 						((u4bRegValue & 0xff) << 8)));
 	}
 
-	//=============================================================================
-//by amy for antenna
-	//=============================================================================
-//{by amy 080312
-	// Config Sw/Hw  Combinational Antenna Diversity. Added by Roger, 2008.02.26.
+	/*
+	=============================================================================
+	by amy for antenna
+	=============================================================================
+	*/
+/* {by amy 080312 */
+	/* Config Sw/Hw  Combinational Antenna Diversity. Added by Roger, 2008.02.26.	*/
 	SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
-//by amy 080312}
-//by amy for antenna
+/* by amy 080312} */
+/* by amy for antenna */
 }
 
 
@@ -780,13 +753,13 @@ UpdateInitialGain(
 {
 	struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 
-	//lzm add 080826
-	if(priv->eRFPowerState != eRfOn)
-	{
-		//Don't access BB/RF under disable PLL situation.
-		//RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
-		// Back to the original state
-		priv->InitialGain= priv->InitialGainBackUp;
+	/* lzm add 080826 */
+	if (priv->eRFPowerState != eRfOn)	{
+		/*	Don't access BB/RF under disable PLL situation.
+			RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
+			Back to the original state
+		*/
+		priv->InitialGain = priv->InitialGainBackUp;
 		return;
 	}
 
@@ -846,11 +819,11 @@ UpdateInitialGain(
 		break;
 	}
 }
-//
-//	Description:
-//		Tx Power tracking mechanism routine on 87SE.
-// 	Created by Roger, 2007.12.11.
-//
+/*
+	Description:
+		Tx Power tracking mechanism routine on 87SE.
+	Created by Roger, 2007.12.11.
+*/
 void
 InitTxPwrTracking87SE(
 	struct net_device *dev
@@ -860,7 +833,7 @@ InitTxPwrTracking87SE(
 
 	u4bRfReg = RF_ReadReg(dev, 0x02);
 
-	// Enable Thermal m