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authorMark Brown <broonie@linaro.org>2013-09-01 13:49:07 +0100
committerMark Brown <broonie@linaro.org>2013-09-01 13:49:07 +0100
commit278ac33bbd8b3ff70f9518665c892c1b6f5625b7 (patch)
tree5a5a1e6d7ae2d4105774c55d9c5cd0ee25bd6ce1
parent85cac431329bd09f7d30d489591d7af0d658b008 (diff)
parenta110f93d8b4672c4ad18d911f62b9e861010e83b (diff)
Merge remote-tracking branch 'spi/topic/quad' into spi-next
-rw-r--r--Documentation/devicetree/bindings/spi/spi-bus.txt10
-rw-r--r--drivers/spi/spi.c77
2 files changed, 47 insertions, 40 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
index 296015e3c63..800dafe5b01 100644
--- a/Documentation/devicetree/bindings/spi/spi-bus.txt
+++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -55,6 +55,16 @@ contain the following properties.
chip select active high
- spi-3wire - (optional) Empty property indicating device requires
3-wire mode.
+- spi-tx-bus-width - (optional) The bus width(number of data wires) that
+ used for MOSI. Defaults to 1 if not present.
+- spi-rx-bus-width - (optional) The bus width(number of data wires) that
+ used for MISO. Defaults to 1 if not present.
+
+Some SPI controllers and devices support Dual and Quad SPI transfer mode.
+It allows data in SPI system transfered in 2 wires(DUAL) or 4 wires(QUAD).
+Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
+only 1(SINGLE), 2(DUAL) and 4(QUAD).
+Dual/Quad mode is not allowed when 3-wire mode is used.
If a gpio chipselect is used for the SPI slave the gpio number will be passed
via the cs_gpio
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 6ef349f82b5..9e039c60c06 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -886,48 +886,44 @@ static void of_register_spi_devices(struct spi_master *master)
spi->mode |= SPI_3WIRE;
/* Device DUAL/QUAD mode */
- prop = of_get_property(nc, "spi-tx-nbits", &len);
- if (!prop || len < sizeof(*prop)) {
- dev_err(&master->dev, "%s has no 'spi-tx-nbits' property\n",
- nc->full_name);
- spi_dev_put(spi);
- continue;
- }
- switch (be32_to_cpup(prop)) {
- case SPI_NBITS_SINGLE:
- break;
- case SPI_NBITS_DUAL:
- spi->mode |= SPI_TX_DUAL;
- break;
- case SPI_NBITS_QUAD:
- spi->mode |= SPI_TX_QUAD;
- break;
- default:
- dev_err(&master->dev, "spi-tx-nbits value is not supported\n");
- spi_dev_put(spi);
- continue;
+ prop = of_get_property(nc, "spi-tx-bus-width", &len);
+ if (prop && len == sizeof(*prop)) {
+ switch (be32_to_cpup(prop)) {
+ case SPI_NBITS_SINGLE:
+ break;
+ case SPI_NBITS_DUAL:
+ spi->mode |= SPI_TX_DUAL;
+ break;
+ case SPI_NBITS_QUAD:
+ spi->mode |= SPI_TX_QUAD;
+ break;
+ default:
+ dev_err(&master->dev,
+ "spi-tx-bus-width %d not supported\n",
+ be32_to_cpup(prop));
+ spi_dev_put(spi);
+ continue;
+ }
}
- prop = of_get_property(nc, "spi-rx-nbits", &len);
- if (!prop || len < sizeof(*prop)) {
- dev_err(&master->dev, "%s has no 'spi-rx-nbits' property\n",
- nc->full_name);
- spi_dev_put(spi);
- continue;
- }
- switch (be32_to_cpup(prop)) {
- case SPI_NBITS_SINGLE:
- break;
- case SPI_NBITS_DUAL:
- spi->mode |= SPI_RX_DUAL;
- break;
- case SPI_NBITS_QUAD:
- spi->mode |= SPI_RX_QUAD;
- break;
- default:
- dev_err(&master->dev, "spi-rx-nbits value is not supported\n");
- spi_dev_put(spi);
- continue;
+ prop = of_get_property(nc, "spi-rx-bus-width", &len);
+ if (prop && len == sizeof(*prop)) {
+ switch (be32_to_cpup(prop)) {
+ case SPI_NBITS_SINGLE:
+ break;
+ case SPI_NBITS_DUAL:
+ spi->mode |= SPI_RX_DUAL;
+ break;
+ case SPI_NBITS_QUAD:
+ spi->mode |= SPI_RX_QUAD;
+ break;
+ default:
+ dev_err(&master->dev,
+ "spi-rx-bus-width %d not supported\n",
+ be32_to_cpup(prop));
+ spi_dev_put(spi);
+ continue;
+ }
}
/* Device speed */
@@ -1480,6 +1476,7 @@ static int __spi_async(struct spi_device *spi, struct spi_message *message)
return -EINVAL;
if (xfer->speed_hz && master->max_speed_hz &&
xfer->speed_hz > master->max_speed_hz)
+ return -EINVAL;
if (xfer->tx_buf && !xfer->tx_nbits)
xfer->tx_nbits = SPI_NBITS_SINGLE;