1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
|
; Test that intrinsic declarations are read back correctly.
; RUN: llvm-as < %s | pnacl-freeze --pnacl-version=1 | pnacl-thaw \
; RUN: | llvm-dis - | FileCheck %s -check-prefix=TD
; RUN: llvm-as < %s | pnacl-freeze --pnacl-version=2 | pnacl-thaw \
; RUN: | llvm-dis - | FileCheck %s -check-prefix=TD
declare i8* @llvm.stacksave()
declare void @llvm.stackrestore(i8*)
declare i8* @llvm.nacl.read.tp()
declare void @llvm.nacl.longjmp(i8*, i32)
declare void @llvm.nacl.setjmp(i8*)
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1)
declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1)
declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1)
declare i32 @llvm.nacl.atomic.load.i32(i32*, i32)
declare i64 @llvm.nacl.atomic.load.i64(i64*, i32)
declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32)
declare i64 @llvm.nacl.atomic.cmpxchg.i64(i64*, i64, i64, i32, i32)
declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32)
declare void @llvm.nacl.atomic.store.i64(i64, i64*, i32)
declare i32 @llvm.nacl.atomic.rmw.i32(i32, i32*, i32, i32)
declare i64 @llvm.nacl.atomic.rmw.i64(i32, i64*, i64, i32)
declare i1 @llvm.nacl.atomic.is.lock.free(i32, i8*)
; TD: declare i8* @llvm.stacksave()
; TD: declare void @llvm.stackrestore(i8*)
; TD: declare i8* @llvm.nacl.read.tp()
; TD: declare void @llvm.nacl.longjmp(i8*, i32)
; TD: declare void @llvm.nacl.setjmp(i8*)
; TD: declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1)
; TD: declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1)
; TD: declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1)
; TD: declare i32 @llvm.nacl.atomic.load.i32(i32*, i32)
; TD: declare i64 @llvm.nacl.atomic.load.i64(i64*, i32)
; TD: declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32)
; TD: declare i64 @llvm.nacl.atomic.cmpxchg.i64(i64*, i64, i64, i32, i32)
; TD: declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32)
; TD: declare void @llvm.nacl.atomic.store.i64(i64, i64*, i32)
; TD: declare i32 @llvm.nacl.atomic.rmw.i32(i32, i32*, i32, i32)
; TD: declare i64 @llvm.nacl.atomic.rmw.i64(i32, i64*, i64, i32)
; TD: declare i1 @llvm.nacl.atomic.is.lock.free(i32, i8*)
|
