1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
|
/* Title: PhyRegAlloc.h -*- C++ -*-
Author: Ruchira Sasanka
Date: Aug 20, 01
Purpose: This is the main entry point for register allocation.
Notes:
=====
* RegisterClasses: Each RegClass accepts a
MachineRegClass which contains machine specific info about that register
class. The code in the RegClass is machine independent and they use
access functions in the MachineRegClass object passed into it to get
machine specific info.
* Machine dependent work: All parts of the register coloring algorithm
except coloring of an individual node are machine independent.
Register allocation must be done as:
FunctionLiveVarInfo LVI(*FunctionI ); // compute LV info
LVI.analyze();
TargetMachine &target = ....
PhyRegAlloc PRA(*FunctionI, target, &LVI); // allocate regs
PRA.allocateRegisters();
*/
#ifndef PHY_REG_ALLOC_H
#define PHY_REG_ALLOC_H
#include "llvm/CodeGen/RegClass.h"
#include "llvm/CodeGen/LiveRangeInfo.h"
#include <deque>
class MachineCodeForMethod;
class MachineRegInfo;
class FunctionLiveVarInfo;
class MachineInstr;
namespace cfg { class LoopInfo; }
//----------------------------------------------------------------------------
// Class AddedInstrns:
// When register allocator inserts new instructions in to the existing
// instruction stream, it does NOT directly modify the instruction stream.
// Rather, it creates an object of AddedInstrns and stick it in the
// AddedInstrMap for an existing instruction. This class contains two vectors
// to store such instructions added before and after an existing instruction.
//----------------------------------------------------------------------------
struct AddedInstrns {
std::deque<MachineInstr*> InstrnsBefore;// Added insts BEFORE an existing inst
std::deque<MachineInstr*> InstrnsAfter; // Added insts AFTER an existing inst
};
typedef std::map<const MachineInstr *, AddedInstrns> AddedInstrMapType;
//----------------------------------------------------------------------------
// class PhyRegAlloc:
// Main class the register allocator. Call allocateRegisters() to allocate
// registers for a Function.
//----------------------------------------------------------------------------
class PhyRegAlloc: public NonCopyable {
std::vector<RegClass *> RegClassList; // vector of register classes
const TargetMachine &TM; // target machine
const Function *Meth; // name of the function we work on
MachineCodeForMethod &mcInfo; // descriptor for method's native code
FunctionLiveVarInfo *const LVI; // LV information for this method
// (already computed for BBs)
LiveRangeInfo LRI; // LR info (will be computed)
const MachineRegInfo &MRI; // Machine Register information
const unsigned NumOfRegClasses; // recorded here for efficiency
AddedInstrMapType AddedInstrMap; // to store instrns added in this phase
AddedInstrns AddedInstrAtEntry; // to store instrns added at entry
cfg::LoopInfo *LoopDepthCalc; // to calculate loop depths
ReservedColorListType ResColList; // A set of reserved regs if desired.
// currently not used
public:
PhyRegAlloc(Function *F, const TargetMachine& TM, FunctionLiveVarInfo *Lvi,
cfg::LoopInfo *LoopDepthCalc);
~PhyRegAlloc();
// main method called for allocating registers
//
void allocateRegisters();
// access to register classes by class ID
//
const RegClass* getRegClassByID(unsigned int id) const {
return RegClassList[id];
}
RegClass* getRegClassByID(unsigned int id) {
return RegClassList[id]; }
private:
//------- ------------------ private methods---------------------------------
void addInterference(const Value *Def, const ValueSet *LVSet,
bool isCallInst);
void addInterferencesForArgs();
void createIGNodeListsAndIGs();
void buildInterferenceGraphs();
void setCallInterferences(const MachineInstr *MInst,
const ValueSet *LVSetAft );
void move2DelayedInstr(const MachineInstr *OrigMI,
const MachineInstr *DelayedMI );
void markUnusableSugColors();
void allocateStackSpace4SpilledLRs();
void insertCode4SpilledLR (const LiveRange *LR,
MachineInstr *MInst,
const BasicBlock *BB,
const unsigned OpNum);
inline void constructLiveRanges() { LRI.constructLiveRanges(); }
void colorIncomingArgs();
void colorCallRetArgs();
void updateMachineCode();
void printLabel(const Value *const Val);
void printMachineCode();
friend class UltraSparcRegInfo;
int getUsableUniRegAtMI(RegClass *RC, int RegType,
const MachineInstr *MInst,
const ValueSet *LVSetBef, MachineInstr *&MIBef,
MachineInstr *&MIAft );
int getUnusedUniRegAtMI(RegClass *RC, const MachineInstr *MInst,
const ValueSet *LVSetBef);
void setRelRegsUsedByThisInst(RegClass *RC, const MachineInstr *MInst );
int getUniRegNotUsedByThisInst(RegClass *RC, const MachineInstr *MInst);
void addInterf4PseudoInstr(const MachineInstr *MInst);
};
#endif
|
