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2011-03-18Thumb2 PC-relative loads require a fixup rather than just an immediate.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15- Add "Bitcast" target instruction property for instructions which performEvan Cheng
nothing more than a bitcast. - Teach tablegen to automatically infer "Bitcast" property. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15X86 table-generator and disassembler support for the AVXSean Callanan
instruction set. This code adds support for the VEX prefix and for the YMM registers accessible on AVX-enabled architectures. Instruction table support that enables AVX instructions for the disassembler is in an upcoming patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127644 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14Ignore isCodeGenOnly instructions when generating diassembly tables.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127619 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14Correct small comment order typo.Francois Pichet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12Remove no-longer-correct special case for disasm of ARM BL instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Pseudo-ize the ARM 'B' instruction.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127510 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127509 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Pseudo-ize VMOVDcc and VMOVScc.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127506 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Remove dead code. These ARM instruction definitions don't exist.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127491 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11ARM VDUPfd and VDUPfq can just be patterns. The instruction is the sameJim Grosbach
as for VDUP32d and VDUP32q, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127489 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Remove dead code. These ARM instruction definitions don't exist.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32qJim Grosbach
and VDUPLN32d, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11ARM VREV64df and VREV64qf can just be patterns. The instruction is the sameJim Grosbach
as for VREV64d32 and VREV64q32, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Add missing 'return on failure'. Previously we'd crash after emittingJim Grosbach
the diagnostic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Teach TableGen to pre-calculate register enum values when creating theJim Grosbach
CodeGenRegister entries. Use this information to more intelligently build the literal register entires in the DAGISel matcher table. Specifically, use a single-byte OPC_EmitRegister entry for registers with a value of less than 256 and OPC_EmitRegister2 entry for registers with a larger value. rdar://9066491 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127456 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Make the register enum value part of the CodeGenRegister struct.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127448 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127447 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127446 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127445 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10Properly pseudo-ize MOVCCr and MOVCCs.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127434 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10Memory barrier instructions don't need special handling in tblgen anymore.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127419 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-07Rename the narrow shift right immediate operands to "shr_imm*" operands. AlsoBill Wendling
expand the testing of the narrowing shift right instructions. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03TableGen should not ignore BX instructions for the ARM disassembler. pr9368.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126931 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03pr9367: Add missing predicated BLX instructions.Bob Wilson
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126915 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02Teach the clang attribute emitter about InheritableParamAttr.John McCall
Intended to be atomic with clang r126828. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126827 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-01trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126733 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-01Generalize the register matching code in DAGISel a bit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126731 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-01Narrow right shifts need to encode their immediates differently from a normalBill Wendling
shift. 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-26A new TableGen feature! (Not turned on just yet.)Bill Wendling
InstAlias<{alias}, {aliasee}>; The InstAlias instruction should be able to go from the MCInst to the {alias}. All of the information is there to match the MCInst with the {aliasee}. From there, it's a simple matter to emit the {alias}, with the correct operands from the {aliasee}. The code this patch generates can be used by the InstPrinter to automatically print out the alias without having to write special C++ code to handle the situation. This is a WIP, and therefore are several limitations. For instance, it cannot handle AsmOperands at the moment. It also doesn't know what to do when two {alias}es match the same {aliasee}. (Currently, it just ignores those two cases and allows the printInstruction method to handle them.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126538 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24In utils/TableGen/ClangSACheckersEmitter.cpp, set the 'Hidden' bit for checkers.Argyrios Kyrtzidis
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126436 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22Implement xgetbv and xsetbv.Rafael Espindola
Patch by Jai Menon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126165 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-20Put targets on folders, if the IDE supports the feature.Oscar Fuentes
Requires CMake 2.8.3 or newer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-18CMake: updated list of tblgen source files.Oscar Fuentes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-18Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for ↵Owen Anderson
fixed-length instruction encodings. A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen like the existing disassembly emitters do. The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove some of the hacks the old one introduced to tblgen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125966 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-17Check that MnemonicAlias doesn't map back to the same string.Joerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125792 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-17Add serialization for Expr* arguments for attributes to clang tablegen files.Sean Hunt
Patch thanks to Zach Anderson. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125721 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-15When tablegen'ing the clang analyzer checkers:Argyrios Kyrtzidis
-Use the tablegen class name for the checker class name. -Mark checker packages as hidden/not hidden. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125558 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-14Add the ClangSACheckersEmitter tablegen backend which will be used for the ↵Argyrios Kyrtzidis
clang static analyzer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125493 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-14Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes
- Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-13Wrap the struct in an anonymous namespace.Argyrios Kyrtzidis
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125452 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-12AsmMatcher custom operand parser failure enhancements.Jim Grosbach
Teach the AsmMatcher handling to distinguish between an error custom-parsing an operand and a failure to match. The former should propogate the error upwards, while the latter should continue attempting to parse with alternative matchers. Update the ARM asm parser accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125426 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-11Tidy out asm matcher .inc output.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125408 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-10Don't return before calling the post-processing function(s).Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125256 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-10Do AsmMatcher operand classification per-opcode.Jim Grosbach
When matching operands for a candidate opcode match in the auto-generated AsmMatcher, check each operand against the expected operand match class. Previously, operands were classified independently of the opcode being handled, which led to difficulties when operand match classes were more complicated than simple subclass relationships. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-07Implement support for custom target specific asm parsing of operands.Bruno Cardoso Lopes
Motivation: Improve the parsing of not usual (different from registers or immediates) operand forms. This commit implements only the generic support. The ARM specific modifications will come next. A table like the one below is autogenerated for every instruction containing a 'ParserMethod' in its AsmOperandClass static const OperandMatchEntry OperandMatchTable[20] = { /* Mnemonic, Operand List Mask, Operand Class, Features */ { "cdp", 29 /* 0, 2, 3, 4 */, MCK_Coproc, Feature_IsThumb|Feature_HasV6 }, { "cdp", 58 /* 1, 3, 4, 5 */, MCK_Coproc, Feature_IsARM }, A matcher function very similar (but lot more naive) to MatchInstructionImpl scans the table. After the mnemonic match, the features are checked and if the "to be parsed" operand index is present in the mask, there's a real match. Then, a switch like the one below dispatch the parsing to the custom method provided in 'ParseMethod': case MCK_Coproc: return TryParseCoprocessorOperandName(Operands); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-04MC/AsmMatcher: Sink ConvertToMCInst into the TargetAsmParser instance, whichDaniel Dunbar
implicitly allows custom conversions to be member functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124908 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-04Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.Jason W Kim
(yes, this is different from R_ARM_CALL) - Adds a new method getARMBranchTargetOpValue() which handles the necessary distinction between the conditional and unconditional br/bl needed for ARM/ELF At least for ARM mode, the needed fixup for conditional versus unconditional br/bl is identical, but the ARM docs and existing ARM tools expect this reloc type... Added a few FIXME's for future naming fixups in ARMInstrInfo.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124895 91177308-0d34-0410-b5e6-96231b3b80d8
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