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2012-10-10misched: Generate IsBuffered flag for machine resources.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165602 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08Move TargetData to DataLayout.Micah Villmow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165403 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05[ms-inline asm] Add a few typedefs to simplify future changes.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165324 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05tblgen: Replace uses of dynamic_cast<XXXRecTy> with dyn_cast<>.Sean Silva
This is a mechanical change of dynamic_cast<> to dyn_cast<>. A number of these uses are actually more like isa<> or cast<>, and will be changed to the semanticaly appropriate one in a future patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03Added instregex support to TableGen subtarget emitter.Andrew Trick
This allows the processor-specific machine model to override selected base opcodes without any fanciness. e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165180 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03TableGen subtarget emitter, nearly first class support for SchedAlias.Andrew Trick
A processor can now arbitrarily alias one SchedWrite onto another. Only the SchedAlias definition need be within the processor model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or transitively refer to another alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165179 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03Cleanup TableGen subtarget emitter.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165178 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03[ms-inline asm] Default to the 'm' constraint. This matches the behavior of theChad Rosier
MSVC compiler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165174 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03tblgen: Migrate llvm-tblgen to new TableGenMain API.Sean Silva
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Fix 80-column violations. Cleanup whitespace in generated code.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-01[ms-inline asm] Add the convertToMapAndConstraints() function that is used toChad Rosier
map constraints and MCInst operands to inline asm operands. This replaces the getMCInstOperandNum() function. The logic to determine the constraints are not in place, so we still default to a register constraint (i.e., "r"). Also, we no longer build the MCInst but rather return just the opcode to get the MCInstrDesc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164979 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-01Merge commit '72f0976c1b91c7ba50dce4d0ad0289dc14d37f81'Derek Schuff
Conflicts: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsSubtarget.cpp
2012-09-27Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. ↵Sylvestre Ledru
See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27Fix a typo 'iff' => 'if'Sylvestre Ledru
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25Merge commit 'bc4021f31eaa97ee52655828da3e3de14a39e4a6'Derek Schuff
Conflicts: lib/MC/MCAssembler.cpp lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/Mips/MipsInstrFPU.td lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp lib/Target/X86/X86ISelLowering.h
2012-09-24Rather then have a wrapper function, have tblgen instantiate the implementation.Chad Rosier
Also remove an unused argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164567 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Rather then have a wrapper function, have tblgen instantiate the implementation.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164548 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-22Machine Model (-schedmodel only). Added SchedAliases.Andrew Trick
Allow subtargets to tie SchedReadWrite types to processor specific sequences or variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164451 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21[ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164420 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Whitespace.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164406 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19Merge commit '020aba0c3b6092e353e133446cb6453f95f0d61b'Derek Schuff
2012-09-19Add in new data types that are used by AMDIL/ANL among others.Micah Villmow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164261 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19Soften the pattern-can-never-match error in TableGen into a warning. This ↵Owen Anderson
pattern can be very useful in cases where you want to define a multiclass that covers both commutative and non-commutative operators (say, add and sub). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164256 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19Remove code for setting the VEX L-bit as a function of operand size from the ↵Craig Topper
code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164204 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19SchedMachineModel: compress the CPU's WriteLatencyTable.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164199 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19Iterate deterministicaly over ClassInfo*'sSean Silva
Fixes an observed instance of nondeterministic TableGen output. Review by Jakob. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164191 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19Iterate deterministically over register classesSean Silva
Fixes an observed instance of nondeterministic TableGen output. Review by Jakob. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164190 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19Refactor Record* by-ID comparator to Record.hSean Silva
This is a generally useful utility; there's no reason to have it hidden in CodeGenDAGPatterns.cpp. Also, rename it to fit the other comparators in Record.h Review by Jakob. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164189 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18Merge commit '8e70b5506ec0d7a6c2740bc89cd1b8f12a78b24f'Derek Schuff
Conflicts: include/llvm/CodeGen/ISDOpcodes.h include/llvm/Target/Target.td include/llvm/Target/TargetLowering.h include/llvm/Target/TargetOpcodes.h lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp lib/Target/Mips/MipsMCInstLower.cpp utils/TableGen/CodeGenTarget.cpp
2012-09-18Make custom operand parsing mnemonic indices use the same mnemonic table as ↵Craig Topper
the match table. Reorder fields in OperandMatchEntry to provide the least amount of padding for in tree targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18Use variable type for index into mnemonic table. Shrinks size of index field ↵Craig Topper
on in tree targets. Saving static data space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164108 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18Replaced ReInitMCSubtargetInfo with InitMCProcessor.Andrew Trick
Now where we used to call ReInitMCSubtargetInfo, we actually recompute the same information as InitMCSubtargetInfo instead of only setting the feature bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164105 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18comment typoAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164097 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18TableGen subtarget emitter. Use getSchedClassIdx.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164096 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18TableGen subtarget emitter. Generate resolveSchedClass generated hook for ↵Andrew Trick
resolving instruction variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164095 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18TableGen subtarget emitter. Remove unnecessary header dependence.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164094 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick
model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18Mark asm matcher conversion table as const.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164088 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18Fix typo in comment. No functional change.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17Backout the wrong subtarget emitter fixAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164078 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17Fix release build after revertingAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick
I have to work out the Target/CodeGen header dependencies before putting this back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17InitMCProcessorAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164066 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17comment typoAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen subtarget emitter. Use getSchedClassIdx.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen subtarget emitter. Generate resolveSchedClass generated hook for ↵Andrew Trick
resolving instruction variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164062 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick
model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164061 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen subtarget emitter. Format and emit data tables for the new machine ↵Andrew Trick
model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164060 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen subtarget emitter. Generate data tables for the new machine model.Andrew Trick
Map the CodeGenSchedule object model onto data tables. The structure of the data tables is defined in MC, so for convenience we include MCSchedule.h. The alternative is maintaining a redundant copy of the table structure definitions. Mapping the object model onto data tables is sufficiently complicated that it should not be interleaved with emitting source code. This avoids major problem with the backend for itinerary generation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen subtarget emitter. Emit processor resources for the new machine model.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164058 91177308-0d34-0410-b5e6-96231b3b80d8
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