aboutsummaryrefslogtreecommitdiff
path: root/utils/TableGen/EDEmitter.cpp
AgeCommit message (Expand)Author
2011-08-02ARM: rename addrmode7 to addr_offset_none.Jim Grosbach
2011-07-27Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.Kevin Enderby
2011-07-26Split am2offset into register addend and immediate addend forms, necessary fo...Owen Anderson
2011-07-26ARM parsing and encoding for SVC instruction.Jim Grosbach
2011-07-25ARM assembly parsing and encoding for SSAT16 instruction.Jim Grosbach
2011-07-22ARM SSAT instruction 5-bit immediate handling.Jim Grosbach
2011-07-21Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn n...Owen Anderson
2011-07-21Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowi...Owen Anderson
2011-07-20ARM PKH shift ammount operand printing tweaks.Jim Grosbach
2011-07-19ARM assembly parsing for MOV (immediate).Jim Grosbach
2011-07-13Range checking for CDP[2] immediates.Jim Grosbach
2011-07-13Give the ARM BKPT instruction the right operand type.Jim Grosbach
2011-07-11Resynchronize EDInfo.h and EDEmitter.cpp.Shantonu Sen
2011-07-06Don't require pseudo-instructions to carry encoding information.Jim Grosbach
2011-06-27ARM Assembly support for Thumb mov-immediate.Jim Grosbach
2011-05-31Fix ssat and ssat16 encodings for ARM and Thumb. The bit position valueBruno Cardoso Lopes
2011-05-09Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane...Mon P Wang
2011-04-23Remove unused STL header includes.Jay Foad
2011-03-24Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes
2011-03-18Thumb2 PC-relative loads require a fixup rather than just an immediate.Owen Anderson
2011-03-07Rename the narrow shift right immediate operands to "shr_imm*" operands. AlsoBill Wendling
2011-03-01Narrow right shifts need to encode their immediates differently from a normalBill Wendling
2011-02-14Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes
2011-02-04Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.Jason W Kim
2011-01-26TableGen: PointerLikeRegClass can be accepted to operand.NAKAMURA Takumi
2011-01-18Add support for parsing and encoding ARM's official syntax for the BFI instru...Bruno Cardoso Lopes
2011-01-13Add support to the ARM MC infrastructure to support mcr and friends. This req...Owen Anderson
2011-01-13Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a stepEvan Cheng
2010-12-14Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755Jim Grosbach
2010-12-14The tLDR et al instructions were emitting either a reg/reg or reg/immBill Wendling
2010-12-14Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering ...Owen Anderson
2010-12-13Revert r121721, which broke buildbots.Owen Anderson
2010-12-13Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provid...Owen Anderson
2010-12-13In Thumb2, direct branches can be encoded as either a "short" conditional bra...Owen Anderson
2010-12-13eliminate the Records global variable, patch by Garrison Venn!Chris Lattner
2010-12-10Thumb unconditional branch binary encoding. rdar://8754994Jim Grosbach
2010-12-10Thumb conditional branch binary encodings. rdar://8745367Jim Grosbach
2010-12-09Thumb needs a few different encoding schemes for branch targets. RenameJim Grosbach
2010-12-09The BLX instruction is encoded differently than the BL, because why not? InBill Wendling
2010-12-08Support the "target" encodings for the CB[N]Z instructions.Bill Wendling
2010-12-08Add support for loading from a constant pool.Bill Wendling
2010-12-06Add fixup for Thumb1 BL/BLX instructions.Jim Grosbach
2010-12-01Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADRJim Grosbach
2010-11-30Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. ...Owen Anderson
2010-11-30Add encoding support for Thumb2 PLD and PLI instructions.Owen Anderson
2010-11-30Fix the encoding of VLD4-dup alignment.Bob Wilson
2010-11-18Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the ...Jason W Kim
2010-11-17Proper encoding for VLDM and VSTM instructions. The register lists for theseBill Wendling
2010-11-11ARM fixup encoding for direct call instructions (BL).Jim Grosbach
2010-11-03Break ARM addrmode4 (load/store multiple base address) into its constituentJim Grosbach
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2026-01-12 17:28:18 +0000