| Age | Commit message (Expand) | Author |
|---|
| 2012-11-14 | X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches. | Jim Grosbach |
| 2012-11-08 | Add support of RTM from TSX extension | Michael Liao |
| 2012-10-29 | [ms-inline asm] Add support for the [] operator. Essentially, [expr1][expr2] is | Chad Rosier |
| 2012-10-24 | Tell llvm-mc we're using intel syntax, so we don't have to use directives. | Chad Rosier |
| 2012-10-24 | [ms-inline asm] Add back-end test case for r166632. Make sure we emit the | Chad Rosier |
| 2012-10-13 | X86: Depending on the local semantics of .align this test can also emit a nop... | Benjamin Kramer |
| 2012-10-13 | X86: Disable long nops for all cpus prior to pentiumpro/i686. | Benjamin Kramer |
| 2012-09-19 | llvm/test/MC/X86/x86_nop.s: Make sure -arch=x86 when -mcpu=geode. | NAKAMURA Takumi |
| 2012-09-18 | Add test for r164132. | Roman Divacky |
| 2012-09-10 | Add newline. | Chad Rosier |
| 2012-09-10 | [ms-inline asm] Add support for .att_syntax directive. | Chad Rosier |
| 2012-08-31 | X86: Fix encoding of 'movd %xmm0, %rax' | Jim Grosbach |
| 2012-07-26 | Make l/q suffixes on AVX forms of scalar convert instructions consistent with... | Craig Topper |
| 2012-07-18 | Make x86 asm parser to check for xmm vs ymm for index register in gather inst... | Craig Topper |
| 2012-07-10 | Reverse assembler/disassembler operand order for gather instructions. | Craig Topper |
| 2012-07-03 | Add aliases for pblendvb, blendvpd, and blendvps instructions with the implic... | Craig Topper |
| 2012-06-29 | X86: add more GATHER intrinsics in LLVM | Manman Ren |
| 2012-06-26 | X86: add GATHER intrinsics (AVX2) in LLVM | Manman Ren |
| 2012-06-26 | Remove some duplicate instructions that exist only to given different mnemoni... | Craig Topper |
| 2012-05-29 | Add intrinsics, code gen, assembler and disassembler support for the SSE4a ex... | Benjamin Kramer |
| 2012-04-11 | Add retw and lretw instructions. Also, fix Intel syntax parsing for all | Charles Davis |
| 2012-04-03 | Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo. | Craig Topper |
| 2012-03-21 | Fix generation of the address size override prefix. Add assertions for | Joerg Sonnenberger |
| 2012-03-13 | Change the X86 assembler to not require a segment register on string | Kevin Enderby |
| 2012-03-12 | Added a missing error check for X86 assembly with mismatched base and index | Kevin Enderby |
| 2012-03-09 | Add the missing call to Error when a bad X86 scale expression is parsed. | Kevin Enderby |
| 2012-03-09 | test/MC/X86/lit.local.cfg: Fix up to detect 'X86' in targets. | NAKAMURA Takumi |
| 2012-03-06 | Fix the operand ordering on aliases for shld and shrd. PR12173, part 2. | Eli Friedman |
| 2012-03-05 | Make aliases for shld and shrd match gas. PR12173. | Eli Friedman |
| 2012-02-23 | Updated the llvm-mc disassembler C API to support for the X86 target. | Kevin Enderby |
| 2012-02-19 | Add vmfunc instruction to X86 assembler and disassembler. | Craig Topper |
| 2012-02-18 | Add X86 assembler and disassembler support for AMD SVM instructions. Original... | Craig Topper |
| 2012-02-16 | Replace all instances of dg.exp file with lit.local.cfg, since all tests are ... | Eli Bendersky |
| 2012-01-30 | Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,... | Devang Patel |
| 2012-01-30 | Intel syntax. Support .intel_syntax directive. | Devang Patel |
| 2012-01-27 | Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320] | Devang Patel |
| 2012-01-24 | Intel Syntax: Extend special hand coded logic, to recognize special instructi... | Devang Patel |
| 2012-01-23 | Intel syntax: Robustify parsing of memory operand's displacement experssion. | Devang Patel |
| 2012-01-23 | Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] | Devang Patel |
| 2012-01-23 | Intel syntax: Parse segment registers. | Devang Patel |
| 2012-01-20 | Intel syntax: Robustify register parsing. | Devang Patel |
| 2012-01-20 | Intel syntax: Parse ... PTR [-8] | Devang Patel |
| 2012-01-20 | Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax. | Devang Patel |
| 2012-01-19 | Post process 'and', 'sub' instructions and select better encoding, if available. | Devang Patel |
| 2012-01-19 | Intel syntax: There is no need to create unary expr for simple negative displ... | Devang Patel |
| 2012-01-19 | Post process 'xor', 'or' and 'cmp' instructions and select better encoding, i... | Devang Patel |
| 2012-01-18 | Process instructions after match to select alternative encoding which may be ... | Devang Patel |
| 2012-01-17 | Intel syntax: Fix parser match class to check memory operand size. | Devang Patel |
| 2012-01-17 | Intel syntax: Parse "BYTE PTR [RDX + RCX]" | Devang Patel |
| 2012-01-17 | Intel syntax: Do not unncessarily create plus expression for memory operand d... | Devang Patel |
