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AgeCommit message (Expand)Author
2013-04-30s tightens up the encoding description for ARM post-indexed ldr instructions....Mihai Popa
2013-04-26ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet
2013-04-19ARM: Permit "sp" in ARM variant of STREXD instructionsTim Northover
2013-04-19ARM: permit "sp" in ARM variants of MOVW/MOVT instructionsTim Northover
2013-04-12ARM: Correct printing of pre-indexed operands.Quentin Colombet
2013-04-10ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover
2013-03-28Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when th...Gordon Keiser
2013-03-26Patch by Gordon Keiser!Joe Abbey
2013-02-22Make ARMAsmPrinter generate the correct alignment specifier syntax in instruc...Kristof Beyls
2013-02-14Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls
2012-12-05Added a option to the disassembler to print immediates as hex.Kevin Enderby
2012-11-29Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInstKevin Enderby
2012-10-30ARM: Better disassembly for pc-relative LDR.Jim Grosbach
2012-10-29Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch targetKevin Enderby
2012-10-22Add support for annotated disassembly output for X86 and arm.Kevin Enderby
2012-09-06Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover
2012-09-06Check for invalid alignment values when decoding VLDn/VSTn (single ln) instru...Tim Northover
2012-09-06Use correct part of complex operand to encode VST1 alignment.Tim Northover
2012-08-13ARM: Move Thumb2 tests to Thumb2 test file and fix CHECK lines.Jim Grosbach
2012-08-02Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ...Jiangning Liu
2012-08-02Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.Jiangning Liu
2012-08-02Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu
2012-07-10Fix instruction description of VMOV (between two ARM core registers and two s...Richard Barton
2012-07-02Fix the remaining TCL-style quotes found in the testsuite. This isChandler Carruth
2012-07-02Convert the uses of '|&' to use '2>&1 |' instead, which works on oldChandler Carruth
2012-07-02Convert all tests using TCL-style quoting to use shell-style quoting.Chandler Carruth
2012-06-06Correct decoder for T1 conditional B encodingRichard Barton
2012-05-11Added the missing bit definition for the 4th bit of the STR (post reg) instru...Silviu Baranga
2012-05-03Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby
2012-05-03Fixed disassembler for vstm/vldm ARM VFP instructions.Silviu Baranga
2012-05-02Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.Richard Barton
2012-04-26Specify cpu to unbreak tests.Evan Cheng
2012-04-24Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)Kevin Enderby
2012-04-24Add missing test cases for ARM VLD4 (single 4-element structure to all lanes)Kevin Enderby
2012-04-18Added support for disassembling unpredictable swp/swpb ARM instructions.Silviu Baranga
2012-04-18Fix the bahavior of the disassembler when decoding unpredictable mrs instruct...Silviu Baranga
2012-04-18Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the ...Silviu Baranga
2012-04-18Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocess...Silviu Baranga
2012-04-18Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instruct...Silviu Baranga
2012-04-17Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)Kevin Enderby
2012-04-11Fixed a case of ARM disassembly getting an assert on a bad encodingKevin Enderby
2012-04-11Fix ARM disassembly of VLD instructions with writebacks.  And add test a caseKevin Enderby
2012-04-11Fix a number of problems with ARM fused multiply add/subtract instructions.Evan Cheng
2012-04-05Added support for unpredictable ADC/SBC instructions on ARM, and also fixed s...Silviu Baranga
2012-04-05Added support for handling unpredictable arithmetic instructions on ARM.Silviu Baranga
2012-04-02Added fix in TableGen instruction decoder generation. The decoder now breaks ...Silviu Baranga
2012-03-25Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnuEli Bendersky
2012-03-22Added soft fail checks for the disassembler when decoding some corner cases o...Silviu Baranga
2012-03-22Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDR...Silviu Baranga
2012-03-22Added soft fail cases for the disassembler when decoding MUL instructions on ...Silviu Baranga
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