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2013-02-08DAGCombiner: Constant folding around pre-increment loads/storesHal Finkel
Previously, even when a pre-increment load or store was generated, we often needed to keep a copy of the original base register for use with other offsets. If all of these offsets are constants (including the offset which was combined into the addressing mode), then this is clearly unnecessary. This change adjusts these other offsets to use the new incremented address. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174746 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-08Revert 172027 and 174336. Remove diagnostics about over-aligned stack objects.Bob Wilson
Aside from the question of whether we report a warning or an error when we can't satisfy a requested stack object alignment, the current implementation of this is not good. We're not providing any source location in the diagnostics and the current warning is not connected to any warning group so you can't control it. We could improve the source location somewhat, but we can do a much better job if this check is implemented in the front-end, so let's do that instead. <rdar://problem/13127907> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174741 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-08When Mips16 frames grow large, the immediate field may exceed the maximumReed Kotler
allowed size for the instruction. This code uses RegScavenger to fix this. We sometimes need 2 registers for Mips16 so we must handle things differently than how register scavenger is normally used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174696 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600: Add support for SET*_DX10 instructionsTom Stellard
These instructions compare two floating point values and return an integer true (-1) or false (0) value. When compiling code generated by the Mesa GLSL frontend, the SET*_DX10 instructions save us four instructions for most branch decisions that use floating-point comparisons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174609 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600: Add tests for unsupported condition codes.Tom Stellard
All of the le and lt variants are unsupported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174608 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600: Fix assembly name for SETGT_INTTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174607 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07Make sure we call externals from libraries properly when -static.Reed Kotler
For example, when we are doing mips16 hard float or soft float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174583 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07Enable jumps when in -static mode.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174580 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06This is a follow-up on r174446, now taking Atom processors intoEli Bendersky
account. Atoms use LEA for updating SP in prologs/epilogs, and the exact LEA opcode depends on the data model. Also reapplying the test case which was added and then reverted (because of Atom failures), this time specifying explicitly the CPU in addition to the triple. The test case now checks all variations (data mode, cpu Atom vs. Core). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174542 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Implement external weak (ELF) symbols on AArch64Tim Northover
Weakly defined symbols should evaluate to 0 if they're undefined at link-time. This is impossible to do with the usual address generation patterns, so we should use a literal pool entry to materlialise the address. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174518 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Remove this test in the meantime, since it won't pass on Atom. Atom uses leaEli Bendersky
to move the stack pointer in prologs/epilogs. I will fix the test and add it back later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174484 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Attempt to recover gdb bot after r174445.Manman Ren
Failure: undefined symbol 'Lline_table_start0'. Root-cause: we use a symbol subtraction to calculate at_stmt_list, but the line table entries are not dumped in the assembly. Fix: use zero instead of a symbol subtraction for Compile Unit 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174479 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Test for r174446Eli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174464 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Dwarf: support for LTO where a single object file can have multiple line tablesManman Ren
We generate one line table for each compilation unit in the object file. Reviewed by Eric and Kevin. rdar://problem/13067005 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174445 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05[mips] Do not use function CC_MipsN_VarArg unless the function being analyzedAkira Hatanaka
is a vararg function. The original code was examining flag OutputArg::IsFixed to determine whether CC_MipsN_VarArg or CC_MipsN should be called. This is not correct, since this flag is often set to false when the function being analyzed is a non-variadic function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174442 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Reapply r174343, with a fix for a scary DAG combine bug where it failed to ↵Owen Anderson
differentiate between the alignment of the base point of a load, and the overall alignment of the load. This caused infinite loops in DAG combine with the original application of this patch. ORIGINAL COMMIT LOG: When the target-independent DAGCombiner inferred a higher alignment for a load, it would replace the load with one with the higher alignment. However, it did not place the new load in the worklist, which prevented later DAG combines in the same phase (for example, target-specific combines) from ever seeing it. This patch corrects that oversight, and updates some tests whose output changed due to slightly different DAGCombine outputs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174431 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handleJyotsna Verma
zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174429 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Hexagon: Add testcase for post-increment store instructions.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174419 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05[SjLj Prepare] When demoting an invoke instructions to the stack, if the normalChad Rosier
edge is critical, then split it so we can insert the store. rdar://13126179 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174418 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Hexagon: Use multiclass for absolute addressing mode stores.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174412 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Add a test case for PR14750.Jakob Stoklund Olesen
This was fixed by r174402. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174405 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05R600: Add tests for instruction predicatesTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174393 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05R600: Emit function name in the AsmPrinterTom Stellard
Emitting the function name allows us to check for it in the FileCheck tests so we can make sure FileCheck is checking the output of the correct function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174392 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Hexagon: Add V4 compare instructions. Enable relationship mappingJyotsna Verma
for the existing instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174389 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Revert r174343, "When the target-independent DAGCombiner inferred a higher ↵NAKAMURA Takumi
alignment for a load," It caused hangups in compiling clang/lib/Parse/ParseDecl.cpp and clang/lib/Driver/Tools.cpp in stage2 on some hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174374 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Link .ARM.exidx with corresponding text section.Logan Chien
The sh_link in the ELF section header of .ARM.exidx should be filled with the section index of the corresponding text section. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174372 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05This patch that sets the EmitAlias flag in td files Jack Carter
and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05When the target-independent DAGCombiner inferred a higher alignment for a load,Owen Anderson
it would replace the load with one with the higher alignment. However, it did not place the new load in the worklist, which prevented later DAG combines in the same phase (for example, target-specific combines) from ever seeing it. This patch corrects that oversight, and updates some tests whose output changed due to slightly different DAGCombine outputs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174343 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04[Stack Alignment] emit warning instead of a hard errorManman Ren
Per discussion in rdar://13127907, we should emit a hard error only if people write code where the requested alignment is larger than achievable and assumes the low bits are zeros. A warning should be good enough when we are not sure if the source code assumes the low bits are zeros. rdar://13127907 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174336 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04Hexagon: Add V4 combine instructions and some more Def Pats for V2.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174331 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04Disable a couple more vector splat optimizations on PPC.Benjamin Kramer
I didn't see those because the test case used "not grep". FileCheck the test and XFAIL it, preserving the old optimization, so this can be fixed eventually. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174330 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04X86: Open up some opportunities for constant folding by postponing shift ↵Benjamin Kramer
lowering. Fixes PR15141. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174327 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04SelectionDAG: Teach FoldConstantArithmetic how to deal with vectors.Benjamin Kramer
This required disabling a PowerPC optimization that did the following: input: x = BUILD_VECTOR <i32 16, i32 16, i32 16, i32 16> lowered to: tmp = BUILD_VECTOR <i32 8, i32 8, i32 8, i32 8> x = ADD tmp, tmp The add now gets folded immediately and we're back at the BUILD_VECTOR we started from. I don't see a way to fix this currently so I left it disabled for now. Fix some trivially foldable X86 tests too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174325 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-02Remove the (apparently) unnecessary debug info metadata indirection.David Blaikie
The main lists of debug info metadata attached to the compile_unit had an extra layer of metadata nodes they went through for no apparent reason. This patch removes that (& still passes just as much of the GDB 7.5 test suite). If anyone can show evidence as to why these extra metadata nodes are there I'm open to reverting this patch & documenting why they're there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-02Start static relocation implementation for mips16.Reed Kotler
This checkin makes hello world work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174264 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-02rdar://13126763Shuxin Yang
Fix a bug in DAGCombine. The symptom is mistakenly optimizing expression "x + x*x" into "x * 3.0". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174239 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01LLVM enablement for some older PowerPC CPUsBill Schmidt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01Two changes relevant to LEA and x32:David Sehr
1) allows the use of RIP-relative addressing in 32-bit LEA instructions under x86-64 (ILP32 and LP64) 2) separates the size of address registers in 64-bit LEA instructions from control by ILP32/LP64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174208 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01Hexagon: Test case to confirm generation of indexed loads with zero offset.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174196 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01Add explicit triples to AArch64 testsTim Northover
Only Linux is supported at the moment, and other platforms quickly fault. As a result these tests would fail on non-Linux hosts. It may be worth making the tests more generic again as more platforms are supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31R600: Fold clamp, neg, absTom Stellard
Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174099 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31When lowering memcpys to loads and stores, make sure we don't promote alignmentsLang Hames
past the natural stack alignment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31Cherry-pick r174067Derek Schuff
2013-01-31Add AArch64 as an experimental target.Tim Northover
This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31Check and allow floating point registers to select the size of theEric Christopher
register for inline asm. This conforms to how gcc allows for effective casting of inputs into gprs (fprs is already handled). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174008 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31Replace some more greps with FileChecks in testsEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31Rewrite this test properly with a FileCheck instead of grepsEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173997 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30PPC QPX requires a 32-byte aligned stackHal Finkel
On systems which support the QPX vector instructions, the stack must be 32-byte aligned. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173993 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30Forgot the test case before.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173988 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30Add definitions for the PPC a2q core marked as having QPX availableHal Finkel
This is the first commit of a large series which will add support for the QPX vector instruction set to the PowerPC backend. This instruction set is used on the IBM Blue Gene/Q supercomputers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173973 91177308-0d34-0410-b5e6-96231b3b80d8
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