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2011-02-08PostRA antidependence breaker unit test for PR8986.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125091 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-08PostRA antidependence breaker unit test for rdar://8959122.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125090 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-07Fix an obvious typo which caused an isel assertion. rdar://8964854.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-07Reduce test case, smaller is better.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125019 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-07Add codegen support for using post-increment NEON load/store instructions.Bob Wilson
The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using post-increment versions, but all the rest of the NEON load/store instructions should be handled now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125014 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-07Rework some .ARM.attribute work for improved gcc compatibility.Jason W Kim
Unified EmitTextAttribute for both Asm and Obj emission (.cpu only) Added necessary cortex-A8 related attrs for codegen compat tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-05Target/X86: Tweak allocating shadow area (aka home) on Win64. It must be ↵NAKAMURA Takumi
enough for caller to allocate one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-05Move a test that ended up in the wrong place.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124933 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-04Merge .debug_loc entries whenever possible to reduce debug_loc size.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-04Mark that the return is using EAX so that we don't use it for some otherNick Lewycky
purpose. Fixes PR9080! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-04DebugLoc associated with a machine instruction is used to emit location ↵Devang Patel
entries. DebugLoc associated with a DBG_VALUE is used to identify lexical scope of the variable. After register allocation, while inserting DBG_VALUE remember original debug location for the first instruction and reuse it, otherwise dwarf writer may be mislead in identifying the variable's scope. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-03Add XCore intrinsics for resource instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124794 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-03Add -march to fix the bots.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124774 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-03Fix PR9127 by reversing the operands even if they have more then one use.Rafael Espindola
Reversing the operands allows us to fold, but doesn't force us to. Also, at this point the DAG is still being optimized, so the check for hasOneUse is not very precise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124773 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-02Add support for trampolines on the XCore.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-02Given a pair of floating point load and store, if there are no other uses ofEvan Cheng
the load, then it may be legal to transform the load and store to integer load and store of the same width. This is done if the target specified the transformation as profitable. e.g. On arm, this can transform: vldr.32 s0, [] vstr.32 s0, [] to ldr r12, [] str r12, [] rdar://8944252 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124708 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-31Keep track of incoming argument's location while emitting LiveIns.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124611 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-31Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-30Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, ↵Benjamin Kramer
c1+c2) when c1 equals the amount of bits that are truncated off. This happens all the time when a smul is promoted to a larger type. On x86-64 we now compile "int test(int x) { return x/10; }" into movslq %edi, %rax imulq $1717986919, %rax, %rax movq %rax, %rcx shrq $63, %rcx sarq $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax" addl %ecx, %eax This fires 96 times in gcc.c on x86-64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-29Re-apply r124518 with fix. Watch out for invalidated iterator.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124526 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-29Revert r124518. It broke Linux self-host.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124522 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-29Re-commit r124462 with fixes. Tail recursion elim will now dup ret into ↵Evan Cheng
unconditional predecessor to enable TCE on demand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-28Revert r124462. There are a few big regressions that I need to fix first.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124478 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-28Add a triple.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124471 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-28Print the visibility of declarations.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-28- Stop simplifycfg from duplicating "ret" instructions into unconditionalEvan Cheng
branches. PR8575, rdar://5134905, rdar://8911460. - Allow codegen tail duplication to dup small return blocks after register allocation is done. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124462 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27Add a testcase for my last checkin.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124358 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26Target/X86: Tweak win64's tailcall.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124272 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26Fix whitespace.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124270 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-25Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel
intrinisic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-25Don't merge restore with tail call instruction.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124167 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24Speculatively revert r124138.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124142 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel
intrinisic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124138 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24fix a missing shuffle pattern, PR9009. Patch by Artiom Myaskouvskey!Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-22Pass sret arguments through the stack instead of through registers in Sparc ↵Venkatraman Govindaraju
backend. It makes the code generated more compliant with the sparc32 ABI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-22Added ICC, FCC as uses of movcc instruction to generate correct code when ↵Venkatraman Govindaraju
-mattr=v9 is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Sparc backend: Venkatraman Govindaraju
Rename FLUSH to FLUSHW. Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Last round of fixes for movw + movt global address codegen.Evan Cheng
1. Fixed ARM pc adjustment. 2. Fixed dynamic-no-pic codegen 3. CSE of pc-relative load of global addresses. It's now enabled by default for Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123991 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Implement support for byval arguments in Sparc backend.Venkatraman Govindaraju
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Enable support for precise scheduling of the instruction selectionAndrew Trick
DAG. Disable using "-disable-sched-cycles". For ARM, this enables a framework for modeling the cpu pipeline and counting stalls. It also activates several heuristics to drive scheduling based on the model. Scheduling is inherently imprecise at this stage, and until spilling is improved it may defeat attempts to schedule. However, this framework provides greater control over tuning codegen. Although the flag is not target-specific, it should have very little affect on the default scheduler used by x86. The only two changes that affect x86 are: - scheduling a high-latency operation bumps the current cycle so independent operations can have their latency covered. i.e. two independent 4 cycle operations can produce results in 4 cycles, not 8 cycles. - Two operations with equal register pressure impact and no latency-based stalls on their uses will be prioritized by depth before height (height is irrelevant if no stalls occur in the schedule below this point). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Convert -enable-sched-cycles and -enable-sched-hazard to -disableAndrew Trick
flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relativeEvan Cheng
value, the "add pc" must be CSE'ed at the same time. We could follow the same approach as T2 by adding pseudo instructions that combine the ldr + "add pc". But the better approach is to use movw + movt (which I will enable soon), so I'll leave this as a TODO. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Allow sign-extending of i8 and i16 to i128 on SPU. Kalle Raiskila
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123912 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Expand invalid return values for umulo and smulo. Handle these similarlyEric Christopher
to add/sub by doing the normal operation and then checking for overflow afterwards. This generally relies on the DAG handling the later invalid operations as well. Fixes the 64-bit part of rdar://8622122 and rdar://8774702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123908 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Add test.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123906 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Sorry, several patches in one.Evan Cheng
TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Sparc backend: Implements a delay slot filler that attempt to fill delay slotsVenkatraman Govindaraju
with useful instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20If we can, lower the multiply part of a umulo/smulo call to a libcallEric Christopher
with an invalid type then split the result and perform the overflow check normally. Fixes the 32-bit parts of rdar://8622122 and rdar://8774702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Fix debug info for merged global.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18fix rdar://8878965, a regression I introduced with the recentChris Lattner
llvm.objectsize changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123771 91177308-0d34-0410-b5e6-96231b3b80d8
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