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2011-04-12Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARMCameron Zwarich
stores of arguments in the same cache line. This fixes the second half of <rdar://problem/8674845>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129345 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11Add scheduling information for the MBlaze backend.Wesley Peck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11Look pass copies when determining whether hoisting would end up inserting ↵Evan Cheng
more copies. rdar://9266679 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129297 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09look for the verboten argument slot access in any order, thanks to FritsChris Lattner
for pointing this out git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129217 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09Fix a bug where RecursivelyDeleteTriviallyDeadInstructions couldChris Lattner
delete the instruction pointed to by CGP's current instruction iterator, leading to a crash on the testcase. This fixes PR9578. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129200 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09fix two completely broken tests, which were matching due to PR9629.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129195 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09remove a bunch of CHECK lines that aren't checking whatChris Lattner
they thought they were, because alternation was expanding wrong in {{}}'s. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129194 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09have dag combine zap "store undef", which can be formed during call loweringChris Lattner
with undef arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129185 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09don't test for codegen of 'store undef'Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap ↵Evan Cheng
is lowered into a call to the specified trap function at sdisel time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07Add option to emit @llvm.trap as a function call instead of a trap ↵Evan Cheng
instruction. rdar://9249183. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07Added a check in the preRA scheduler for potential interference on aAndrew Trick
induction variable. The preRA scheduler is unaware of induction vars, so we look for potential "virtual register cycles" instead. Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07Fix handling of functions with internal linkage.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal ↵Tanya Lattner
vector type (vectors of size 3). Also included test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07Change -arm-divmod-libcall to a target neutral option.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129045 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for ↵Owen Anderson
folded comparisons, just like ADD and SUB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05These tests no longer require linear scan because reserved register ↵Jakob Stoklund Olesen
coalescing is now universal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Fix one more batch of X86 tests to be register allocation dependent.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128919 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05When dead code elimination removes all but one use, try to fold the single ↵Jakob Stoklund Olesen
def into the remaining use. Rematerialization can leave single-use loads behind that we might as well fold whenever possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128918 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Fix test-llvm failures.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128906 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05ARM doesn't support byval yet. XFAIL this test until it does.Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128891 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Ensure all defs referring to a virtual register are marked dead by ↵Jakob Stoklund Olesen
addRegisterDead(). There can be multiple defs for a single virtual register when they are defining sub-registers. The missing <dead> flag was stopping the inline spiller from eliminating dead code after rematerialization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Print visibility info for external variables.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128887 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Fix up testcase for previous commit.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128870 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Fix register-dependent X86 tests.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128867 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Allow coalescing with reserved physregs in certain cases:Jakob Stoklund Olesen
When a virtual register has a single value that is defined as a copy of a reserved register, permit that copy to be joined. These virtual register are usually copies of the stack pointer: %vreg75<def> = COPY %ESP; GR32:%vreg75 MOV32mr %vreg75, 1, %noreg, 0, %noreg, %vreg74<kill> MOV32mi %vreg75, 1, %noreg, 8, %noreg, 0 MOV32mi %vreg75<kill>, 1, %noreg, 4, %noreg, 0 CALLpcrel32 ... Coalescing these virtual registers early decreases register pressure. Previously, they were coalesced by RALinScan::attemptTrivialCoalescing after register allocation was completed. The lower register pressure causes the mcinst-lowering-cmp0.ll test case to fail because it depends on linear scan spilling a particular register. I am deleting 2008-08-05-SpillerBug.ll because it is counting the number of instructions emitted, and its revision history shows the 'correct' count being edited many times. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Disable the PowerPC/Atomics-64 test.Jakob Stoklund Olesen
The code inserted by PPCTargetLowering::EmitInstrWithCustomInserter for ppc64 is wrong, and I don't know how to fix it. It seems to be using the correct register classes for pointers, but it inserts all 32-bit instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128835 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Fix PowerPC tests to be register allocator independent.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128827 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02ptx: support setp's 4-operand formatChe-Liang Chiou
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128767 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02Do some peephole optimizations to remove pointless VMOVs from Neon to integerCameron Zwarich
registers that arise from argument shuffling with the soft float ABI. These instructions are particularly slow on Cortex A8. This fixes one half of <rdar://problem/8674845>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128759 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01LDRD/STRD instructions should print both Rt and Rt2 in the asm string.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128736 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01Add code for analyzing FP branches. Clean up branch Analysis functions.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128718 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01Add test case.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128707 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01FileCheck'ify test.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128706 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Fix Thumb and Thumb2 tests to be register allocator independent.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128690 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Provide a legal pointer register class when targeting thumb1.Jakob Stoklund Olesen
The LocalStackSlotAllocation pass was creating illegal registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128687 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Fix SystemZ testsJakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128686 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Fix ARM tests to be register allocator independent.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128680 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplierEvan Cheng
accumulator forwarding: vadd d3, d0, d1 vmul d3, d3, d2 => vmul d3, d0, d2 vmla d3, d1, d2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Fix Mips, Sparc, and XCore tests that were dependent on register allocation.Jakob Stoklund Olesen
Add an extra run with -regalloc=basic to keep them honest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128654 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Added support for FP conditional move instructions and fixed bugs in ↵Akira Hatanaka
handling of FP comparisons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128650 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Don't completely eliminate identity copies that also modify super register ↵Jakob Stoklund Olesen
liveness. Turn them into noop KILL instructions instead. This lets the scavenger know when super-registers are killed and defined. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128645 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Mark all uses as <undef> when joining a copy.Jakob Stoklund Olesen
This way, shrinkToUses() will ignore the instruction that is about to be deleted, and we avoid leaving invalid live ranges that SplitKit doesn't like. Fix a misunderstanding in MachineVerifier about <def,undef> operands. The <undef> flag is valid on def operands where it has the same meaning as <undef> on a use operand. It only applies to sub-register defines which also read the full register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Add XCore intrinsics for initializing / starting / synchronizing threads.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128633 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Pick a conservative register class when creating a small live range for remat.Jakob Stoklund Olesen
The rematerialized instruction may require a more constrained register class than the register being spilled. In the test case, the spilled register has been inflated to the DPR register class, but we are rematerializing a load of the ssub_0 sub-register which only exists for DPR_VFP2 registers. The register class is reinflated after spilling, so the conservative choice is only temporary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128610 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30Don't try to create zero-sized stack objects.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128586 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30Add a ARM-specific SD node for VBSL so that forms with a constant first operandCameron Zwarich
can be recognized. This fixes <rdar://problem/9183078>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128584 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. FrontendsEvan Cheng
was lowering them to sext / uxt + mul instructions. Unfortunately the optimization passes may hoist the extensions out of the loop and separate them. When that happens, the long multiplication instructions can be broken into several scalar instructions, causing significant performance issue. Note the vmla and vmls intrinsics are not added back. Frontend will codegen them as intrinsics vmull* + add / sub. Also note the isel optimizations for catching mul + sext / zext are not changed either. First part of rdar://8832507, rdar://9203134 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29Add Neon SINT_TO_FP and UINT_TO_FP lowering from v4i16 to v4f32. FixesCameron Zwarich
<rdar://problem/8875309> and <rdar://problem/9057191>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128492 91177308-0d34-0410-b5e6-96231b3b80d8
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