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2011-04-29Add trunc->branch support, this won't help with clang's i8->i1 truncationsEric Christopher
for bools, but is a start. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130534 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-29Change DwarfCFIException's member variables to track what it actuallyRafael Espindola
emmits: .cfi_personality, .cfi_lsda and the moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130503 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-29Teach Thumb2 isel to fold and->rotr ==> ROR.Andrew Trick
Generalization of Nate Begeman's patch! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-29Combine thumb2-ror tests.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-28Revert r130454; apparently this doesn't actually work.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130462 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-28Fix runline.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130455 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-28Fix a rather obscure crash caused by ARM fast-isel generating code which ↵Eli Friedman
redefines a register. rdar://problem/9338332 . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130454 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-28fast-isel sret calls, try 2. We actually do need to do something on x86-32. ↵Eli Friedman
rdar://problem/9303592 . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130429 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-28Actually revert r130348 correctly.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130418 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-28Revert r130348; causing buildbot issues on x86-32.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130412 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-28Teach dwarf writer to handle complex address expression for .debug_loc entries.Devang Patel
This fixes clang generated blocks' variables' debug info. Radar 9279956. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130373 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-28Fix a silly mistake in r130338.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130360 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-28PTX: support for bitwise operations on predicatesJustin Holewinski
- selection of bitwise preds (AND, OR, XOR) - new bitwise.ll test Patch by Dan Bailey git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-27fast-isel sret. We actually don't need to do anything special on x86. :) ↵Eli Friedman
rdar://problem/9303592 . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130348 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-27Make the fast-isel code for literal 0.0 a bit shorter/faster, since 0.0 is ↵Eli Friedman
common. rdar://problem/9303592 . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130338 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-27If converter was being too cute. It look for root BBs (which don't haveEvan Cheng
successors) and use inverse depth first search to traverse the BBs. However that doesn't work when the CFG has infinite loops. Simply do a linear traversal of all BBs work just fine. rdar://9344645 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130324 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-27Also add <imp-def> operands for defined and dead super-registers when rewriting.Jakob Stoklund Olesen
We cannot rely on the <imp-def> operands added by LiveIntervals in all cases as demonstrated by the test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130313 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-27Fix an edge case involving branches in fast-isel on x86.Eli Friedman
rdar://problem/9303306 . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130272 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-26Be careful about scheduling nodes above previous calls. It increase usages ofEvan Cheng
more callee-saved registers and introduce copies. Only allows it if scheduling a node above calls would end up lessen register pressure. Call operands also has added ABI restrictions for register allocation, so be extra careful with hoisting them above calls. rdar://9329627 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-26This test should be in MC. It breaks with changes to scheduling / register ↵Evan Cheng
allocation so it's being removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130243 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-26Force a triple on this test to unbreak windows buildbots.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-26Fast-isel support for simple inline asms.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130205 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-26Add test for PR9743.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130198 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-26don't emit the symbol name twice for local bss and commonChris Lattner
symbols. For example, don't emit: .comm _i,4,2 ## @i ## @i instead emit: .comm _i,4,2 ## @i git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-25Make this test disable fast isel as it's not needed.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130165 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-25Lower BlockAddress node when relocation-model is static.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130131 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-25A dbg.declare may not be in entry block, even if it is referring to an ↵Devang Patel
incoming argument. However, It is appropriate to emit DBG_VALUE referring to this incoming argument in entry block in MachineFunction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130129 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-25Make tests more useful.Benjamin Kramer
lit needs a linter ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130126 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-23Accidental function name mangling.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130050 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-23Thumb2 and ARM add/subtract with carry fixes.Andrew Trick
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>. t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the assembly printer correctly prints the 's' suffix. Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags. Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS. Fixes ARM SBC lowering to check for live carry (potential bug). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130048 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-23whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-23test/CodeGen/X86/shrink-compare.ll: Relax expressions for Win64.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130039 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22Recommit the fix for rdar://9289512 with a couple tweaks toChris Lattner
fix bugs exposed by the gcc dejagnu testsuite: 1. The load may actually be used by a dead instruction, which would cause an assert. 2. The load may not be used by the current chain of instructions, and we could move it past a side-effecting instruction. Change how we process uses to define the problem away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22DAGCombine: fold "(zext x) == C" into "x == (trunc C)" if the trunc is lossless.Benjamin Kramer
On x86 this allows to fold a load into the cmp, greatly reducing register pressure. movzbl (%rdi), %eax cmpl $47, %eax -> cmpb $47, (%rdi) This shaves 8k off gcc.o on i386. I'll leave applying the patch in README.txt to Chris :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22X86: Try to use a smaller encoding by transforming (X << C1) & C2 into (X & ↵Benjamin Kramer
(C2 >> C1)) & C1. (Part of PR5039) This tends to happen a lot with bitfield code generated by clang. A simple example for x86_64 is uint64_t foo(uint64_t x) { return (x&1) << 42; } which used to compile into bloated code: shlq $42, %rdi ## encoding: [0x48,0xc1,0xe7,0x2a] movabsq $4398046511104, %rax ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00] andq %rdi, %rax ## encoding: [0x48,0x21,0xf8] ret ## encoding: [0xc3] with this patch we can fold the immediate into the and: andq $1, %rdi ## encoding: [0x48,0x83,0xe7,0x01] movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] shlq $42, %rax ## encoding: [0x48,0xc1,0xe0,0x2a] ret ## encoding: [0xc3] It's possible to save another byte by using 'andl' instead of 'andq' but I currently see no way of doing that without making this code even more complicated. See the TODOs in the code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22In Thumb2 mode, lower frame indix references to:Evan Cheng
add <rd>, sp, #<imm8> ldr <rd>, [sp, #<imm8>] When the offset from sp is multiple of 4 and in range of 0-1020. This saves code size by utilizing 16-bit instructions. rdar://9321541 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-21Fix DWARF description of Q registers.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129952 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-21Fix DWARF description of S registers.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-21Test case for r129922Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129934 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-21Revert r1296656, "Fix rdar://9289512 - not folding load into compare at -O0...",Daniel Dunbar
which broke a couple GCC test suite tests at -O0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129914 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-21ptx: fix parameter orderingChe-Liang Chiou
This patch depends on the prior fix r129908 that changes to use std::find, rather than std::binary_search, on unordered array. Patch by Dan Bailey git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129909 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Remove -use-divmod-libcall. Let targets opt in when they are available.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Un-XFAIL this test for ARM. <rdar://problem/7662569>Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129875 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20PTX: Add intrinsics to list of built-in intrinsics, which allows them to beJustin Holewinski
used by Clang. To help Clang integration, the PTX target has been split into two targets: ptx32 and ptx64, depending on the desired pointer size. - Add GCCBuiltin class to all intrinsics - Split PTX target into ptx32 and ptx64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Rewrite the expander for umulo/smulo to remember to sign extend the inputEric Christopher
manually and pass all (now) 4 arguments to the mul libcall. Add a new ExpandLibCall for just this (copied gratuitously from type legalization). Fixes rdar://9292577 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129842 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19llc: Eliminate a use of getDarwinMajorNumber().Daniel Dunbar
- As before, there is a minor semantic change here (evidenced by the test change) for Darwin triples that have no version component. I debated changing the default behavior of isOSVersionLT, but decided it made more sense for triples to be explicit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129805 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19CodeGen: Eliminate a use of getDarwinMajorNumber().Daniel Dunbar
- There is a minor semantic change here (evidenced by the test change) for Darwin triples that have no version component. I debated changing the default behavior of isOSVersionLT, but decided it made more sense for triples to be explicit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129802 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19This patch combines several changes from Evan Cheng for rdar://8659675.Bob Wilson
Making use of VFP / NEON floating point multiply-accumulate / subtraction is difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Enable these fp vmlx codegen changes for Cortex-A9. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129775 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Add -mcpu=cortex-a9-mp. It's cortex-a9 with MP extension. rdar://8648637.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129774 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Avoid some 's' 16-bit instruction which partially update CPSRBob Wilson
(and add false dependency) when it isn't dependent on last CPSR defining instruction. rdar://8928208 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129773 91177308-0d34-0410-b5e6-96231b3b80d8
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