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2011-06-29Don't depend on the optimization reverted in r134067.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134068 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29Revert a part of r126557 which could create unschedulable DAGs.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134067 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28Clean up the handling of the x87 fp stack to make it more robust.Jakob Stoklund Olesen
Drop the FpMov instructions, use plain COPY instead. Drop the FpSET/GET instruction for accessing fixed stack positions. Instead use normal COPY to/from ST registers around inline assembly, and provide a single new FpPOP_RETVAL instruction that can access the return value(s) from a call. This is still necessary since you cannot tell from the CALL instruction alone if it returns anything on the FP stack. Teach fast isel to use this. This provides a much more robust way of handling fixed stack registers - we can tolerate arbitrary FP stack instructions inserted around calls and inline assembly. Live range splitting could sometimes break x87 code by inserting spill code in unfortunate places. As a bonus we handle floating point inline assembly correctly now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28Implement ISD::VAARG lowering on PPC32.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28FileCheckize a couple of tests.Jakob Stoklund Olesen
Also and add a test for popping dead return values and avoid testing the spill precision. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28FileCheck-ize a test that had the strangest TCL quote I've seen yet: anChandler Carruth
opening single quote with no closing single quote, and with {} quotes "inside" of it. This broke some of our tools that scrape test cases. Also, while here, make the test actually assert what the comment says it asserts. This was essentially authored by Nick Lewycky, and merely typed in by myself. Let me know if this is still missing the mark, but the previous test only succeeded due to the improper quoting preventing *anything* from matching the grep -- it had a '4(%...)' sequence in the output! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133980 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Remove the experimental (and unused) pre-ra splitting pass. Greedy regalloc ↵Evan Cheng
can split live ranges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133962 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27During bottom up fast-isel, instructions emitted to materalize registers are ↵Devang Patel
at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Allow lr in the register options here.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Move all inline-asm-fpstack tests to a single file.Jakob Stoklund Olesen
Also fix some of the tests that were actually testing wrong behavior - An input operand in {st} is only popped by the inline asm when {st} is also in the clobber list. The original bug reports all had ~{st} clobbers as they should. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133916 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25PTX: corrected tests that were failingDan Bailey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133875 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25PTX: Reverting implementation of i8.Dan Bailey
The .b8 operations in PTX are far more limiting than I first thought. The mov operation isn't even supported, so there's no way of converting a .pred value into a .b8 without going via .b16, which is not sensible. An improved implementation needs to use the fact that loads and stores automatically extend and truncate to implement support for EXTLOAD and TRUNCSTORE in order to correctly support boolean values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25Test case for r133858 (tail call optimize in the presence of byval).Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Handle debug info for i128 constants.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133821 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24PTX: Add support for i8 type and introduce associated .b8 registersDan Bailey
The i8 type is required for boolean values, but can only use ld, st and mov instructions. The i1 type continues to be used for predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24The Neon VCVT (between floating-point and fixed-point, Advanced SIMD) Chad Rosier
instructions can be used to match combinations of multiply/divide and VCVT (between floating-point and integer, Advanced SIMD). Basically the VCVT immediate operand that specifies the number of fraction bits corresponds to a floating-point multiply or divide by the corresponding power of 2. For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a combination of VMUL and VCVT (floating-point to integer) as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3 Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a combinations of VCVT (integer to floating-point) and VDIV as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vcvt.f32.s32 d16, d16 vdiv.f32 d16, d17, d16 becomes: vcvt.f32.s32 d16, d16, #3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Change the chain input of nodes that load the address of a function. This changeAkira Hatanaka
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a pre-existing node instead of redundantly create a new node every time it is called. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Prevent generation of redundant addiu instructions that compute address of Akira Hatanaka
static variables or functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133803 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23PTX: Always use registers for return values, but use .param space for deviceJustin Holewinski
parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23PTX: Fixup test cases for device param changesJustin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22lit support for REQUIRES: asserts.Andrew Trick
Take #2. Don't piggyback on the existing config.build_mode. Instead, define a new lit feature for each build feature we need (currently just "asserts"). Teach both autoconf'd and cmake'd Makefiles to define this feature within test/lit.site.cfg. This doesn't require any lit harness changes and should be more robust across build systems. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22Reenable tail duplication of bb with just an unconditional jump, butRafael Espindola
don't remove blocks that have their address taken. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133659 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22Needs a triple.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133634 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22Emit trailing padding on constant vectors when TargetData says that the vectorNick Lewycky
is larger than the sum of the elements (including per-element padding). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22PTX: Add signed integer comparisonsJustin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133599 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22PTX: Add .address_size directive if PTX version >= 2.3Justin Holewinski
Patch by Wei-Ren Chen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133589 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22Test case for r133560.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21Revert r133452: "Emit movq for 64-bit register to XMM register moves..."Bob Wilson
This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using the integrated assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133524 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21Add support for sadd.with.overflow and uadd.with.overflow intrinsics to the ↵Anna Zaks
CBackend by emitting definitions for each intrinsic that occurs in the module. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133522 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21Teach dag combine to match halfword byteswap patterns.Evan Cheng
1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8) => (bswap x) >> 16 2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8)) => (rotl (bswap x) 16) This allows us to eliminate most of the def : Pat patterns for ARM rev16 revsh instructions. It catches many more cases for ARM and x86. rdar://9609108 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133503 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21Re-apply 132758 and 132768 which were speculatively reverted in 132777. Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20PTX: Fix conversion between predicates and value typesJustin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133454 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20Emit movq for 64-bit register to XMM register moves, but continue to acceptNick Lewycky
movd when assembling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133452 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20Don't apply on PPC64 the 32bit ADDIC optimizations as there's no overflowRoman Divacky
with 32bit values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133439 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20Fix PromoteIntRes_TRUNCATE: Add support for cases where theNadav Rotem
source vector type is to be split while the target vector is to be promoted. (eg: <4 x i64> -> <4 x i8> ) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-19Update test.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133390 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-19Reduce the runtime of the test. Keep only the interesting cases.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133381 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-19Remove support for parsing the "type i32" syntax for defining a numberedChris Lattner
top level type without a specified number. This syntax isn't documented and blocks forward progress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133371 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18rip out a ton of intrinsic modernization logic from AutoUpgrade.cpp, which isChris Lattner
for pre-2.9 bitcode files. We keep x86 unaligned loads, movnt, crc32, and the target indep prefetch change. As usual, updating the testsuite is a PITA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18Switch ARM to using AltOrders instead of MethodBodies.Jakob Stoklund Olesen
This slightly changes the GPR allocation order on Darwin where R9 is not a callee-saved register: Before: %R0 %R1 %R2 %R3 %R12 %R9 %LR %R4 %R5 %R6 %R8 %R10 %R11 After: %R0 %R1 %R2 %R3 %R9 %R12 %LR %R4 %R5 %R6 %R8 %R10 %R11 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133326 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18Moved to the right place.Galina Kistanova
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133324 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18Fix UMULO support for 2x register width to allow the fullEric Christopher
range without a libcall to a new mulo<mode> libcall that we'd have to create. Finishes the rest of rdar://9090077 and rdar://9210061 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133318 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17Fix a bug in the type-lowering of integer-promoted elements. Add a check thatNadav Rotem
the newly created simple type is valid before checking its legality. Re-commit the test file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133291 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17Add an alternative rev16 pattern. We should figure out a better way to ↵Evan Cheng
handle these complex rev patterns. rdar://9609108 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133289 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17Lower multiply with overflow checking to __mulo<mode>Eric Christopher
calls if we haven't been able to lower them any other way. Fixes rdar://9090077 and rdar://9210061 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133288 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17est 2008-06-04-indirectmem.ll is X86-specific. Move to X86 folder.Galina Kistanova
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133275 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17Stop accepting and ignoring attributes in function types. Attributes are ↵Chris Lattner
applied to functions and call/invokes, not to types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133266 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17Fix a few places where 32bit instructions/registerset were used on PPC64.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133260 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17PTX: Adjust rounding modesJustin Holewinski
* rounding modes for fp add, mul, sub now use .rn * float -> int rounding correctly uses .rzi not .rni * 32bit fdiv for sm13 uses div.rn (instead of div.approx) * 32bit fdiv for sm10 now uses div (instead of div.approx) Approx is not IEEE 754 compatible (and should be optionally set by a flag to the backend instead). The .rn rounding modifier is the PTX default anyway, but it's better to be explicit. All these modifiers should be available by using __fmul_rz functions for example, but support will need to be added for this in the backend. Patch by Dan Bailey git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133253 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17make the asmparser reject function and type redefinitions. 'Merging' hasn't ↵Chris Lattner
been needed since llvm-gcc 3.4 days. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133248 91177308-0d34-0410-b5e6-96231b3b80d8
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