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AgeCommit message (Expand)Author
2011-08-31Fix (movhps load) lowering / pattern to match more cases. rdar://10050549Evan Cheng
2011-08-31Some minor cleanups for r138845.Eli Friedman
2011-08-31Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.Eli Friedman
2011-08-31Fix test typo.Benjamin Kramer
2011-08-30Add a triple.Rafael Espindola
2011-08-30Some test code to check if correct code is being generated.Rafael Espindola
2011-08-30Set CR1EQ only when lowering vararg floating arguments (not any varargRoman Divacky
2011-08-30Change ARM / Thumb2 addc / adde and subc / sube modeling to use physicalEvan Cheng
2011-08-29Explicitly zero out parts of a vector which are required to be zero by the al...Eli Friedman
2011-08-29Add testcase for r138746.Owen Anderson
2011-08-28Fix PR5329: pay attention to constructor/destructor priorityDuncan Sands
2011-08-27Update to new EH scheme.Bill Wendling
2011-08-27Cannot have an llvm.eh.exception call in a non-landing pad block.Bill Wendling
2011-08-26Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.Eli Friedman
2011-08-26Revert r138606 until LowerInvoke has been converted to the new EH scheme.Bill Wendling
2011-08-26Atomic load/store on ARM/Thumb.Eli Friedman
2011-08-25Update to the new EH scheme.Bill Wendling
2011-08-25Add support for AVX 256-bit version of MOVDDUP!Bruno Cardoso Lopes
2011-08-25ARM fix for missing implicit operands on ldmia_ret.Andrew Trick
2011-08-25LSR wants to split the landing pad's critical edge. Let it do it, but use theBill Wendling
2011-08-25Add support for 256-bit versions of VSHUFPD and VSHUFPS.Bruno Cardoso Lopes
2011-08-24Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient i...Eli Friedman
2011-08-24Basic tests for atomic load and store on x86.Eli Friedman
2011-08-24Add Uses=[SP] to call instructions. This fixes a miscompilation with aRichard Osborne
2011-08-24Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid cos...Craig Topper
2011-08-23Fix a nasty bug where a v4i64 was being wrong emitted with 32-bitBruno Cardoso Lopes
2011-08-23PerformSubCombine to work on integers larger than i128. Fixes a crasher.Nick Lewycky
2011-08-23Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit one...Craig Topper
2011-08-23Introduce a pass to insert vzeroupper instructions to avoid AVX toBruno Cardoso Lopes
2011-08-22Add support for breaking 256-bit int VETCC into two 128-bit ones,Bruno Cardoso Lopes
2011-08-20With the fix in r138164: "Add <imp-def> operands to QQ and QQQQ stack loads."Chad Rosier
2011-08-20VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.Chad Rosier
2011-08-19Do not use named md nodes to track variables that are completely optimized. T...Devang Patel
2011-08-19Use regex to remove false dependencies on register allocation.Jim Grosbach
2011-08-19Update tests.Jim Grosbach
2011-08-19Add test case for r138018.Jakob Stoklund Olesen
2011-08-18Use subword loads instead of a 4-byte load when the size of a structure (or aAkira Hatanaka
2011-08-18FastISel: avoid function calls between the materialization of the constant an...Ivan Krasin
2011-08-18Thumb assembly parsing and encoding for LDM instruction.Jim Grosbach
2011-08-18Add intrinsics for SETEV, GETED, GETET.Richard Osborne
2011-08-18Cleanup vector logical ops in AVX and add use int versions for simpleBruno Cardoso Lopes
2011-08-17Fix PR10688. Add support for spliting 256-bit vector shifts when theBruno Cardoso Lopes
2011-08-17Thumb assembly parsing and encoding for ADR.Jim Grosbach
2011-08-17Introduce matching patterns for vbroadcast AVX instruction. The idea is toBruno Cardoso Lopes
2011-08-17Update test to not use the scalar type to splat from a loadBruno Cardoso Lopes
2011-08-17Now that we have a canonical way to handle 256-bit splats:Bruno Cardoso Lopes
2011-08-17Add support for ext and ins.Akira Hatanaka
2011-08-16Instead of always leaving the work to the generic legalizer whenBruno Cardoso Lopes
2011-08-16Add test case for r137711.Akira Hatanaka
2011-08-16Fix handling of double precision loads and stores when Mips1 is targeted. Akira Hatanaka
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