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2011-09-10Fixed an assert from:Richard Trieu
assert("not implemented for target shuffle node"); to: assert(0 && "not implemented for target shuffle node"); This causes a test failure in CodeGen/X86/palignr.ll which has been marked as XFAIL for the time being. Test failure filed at PR10901. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139454 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Fix test cases.Akira Hatanaka
Generate code for Mips32r1 unless a Mips32r2 feature is tested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139433 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the ↵Eli Friedman
same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Drop support for Mips1 and Mips2.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Implement vector-select support for avx256. Refactor the vblend ↵Nadav Rotem
implementation to have tablegen match the instruction by the node type git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139400 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Drop support for Allegrex. Allegrex implements a variant of Mips2.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Change default target architecture from Mips1 to Mips32r1 in preparation forAkira Hatanaka
removing support for Mips1 and Mips2. This change and the ones that follow have been discussed with and approved by Bruno. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08Directly point debug info to the stack slot of the arugment, instead of ↵Devang Patel
trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139330 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08Add a AVX version of a simple i64 -> f64 bitcast. This could beBruno Cardoso Lopes
triggered using llc with -O0, which wouldn't let it be folded and expose the lack of this pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08Reapply testcase from r139309!Bruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139318 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08Remove this crashing test, until I figure out what's going wrong hereBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139309 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08Add AVX versions of blend vector operations and fix some issues noticedBruno Cardoso Lopes
in Nadav's r139285 and r139287 commits. 1) Rename vsel.ll to a more descriptive name 2) Change the order of BLEND operands to "Op1, Op2, Cond", this is necessary because PBLENDVB is already used in different places with this order, and it was being emitted in the wrong way for vselect 3) Add AVX patterns and tests for the same SSE41 instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139305 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.Bruno Cardoso Lopes
Triggered using llc -O0. Also fix some SET0PS patterns to their AVX forms and test it on the testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139304 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08This test is already covered by llvm/trunk/test/CodeGen/X86/vsel.llNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139288 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08add a testcase for the previous patchNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139287 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08Add X86-SSE4 codegen support for vector-select.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly ↵Eli Friedman
fix some subtle bugs involving passes which check mayStore()). This isn't exactly ideal, but it is good enough for the moment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07Another forgotten trampoline testcase.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139230 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07Relax the MemOperands on atomics a bit. Fixes -verify-machineinstrs ↵Eli Friedman
failures for atomic laod/store on ARM. (The fix for the related failures on x86 is going to be nastier because we actually need Acquire memoperands attached to the atomic load instrs, etc.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139221 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07While sinking machine instructions, sink matching DBG_VALUEs also otherwise ↵Devang Patel
live debug variable pass will drop DBG_VALUEs on the floor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139208 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06Disable these tests harder. They're XFAIL'd, but that means they still run, andNick Lewycky
these tests all infinitely recurse, bringing my system down into swapping hell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06Fix fall outs from my recent change on how carry bit is modeled during isel.Evan Cheng
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well. Also fix isel hook to correctly set the optional operand. rdar://10073745 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139157 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06Atomic pseudos don't use (as in read) CPSR. They clobber it.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139148 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06Split the init.trampoline intrinsic, which currently combines GCC'sDuncan Sands
init.trampoline and adjust.trampoline intrinsics, into two intrinsics like in GCC. While having one combined intrinsic is tempting, it is not natural because typically the trampoline initialization needs to be done in one function, and the result of adjust trampoline is needed in a different (nested) function. To get around this llvm-gcc hacks the nested function lowering code to insert an additional parent variable holding the adjust.trampoline result that can be accessed from the child function. Dragonegg doesn't have the luxury of tweaking GCC code, so it stored the result of adjust.trampoline in the memory GCC set aside for the trampoline itself (this is always available in the child function), and set up some new memory (using an alloca) to hold the trampoline. Unfortunately this breaks Go which allocates trampoline memory on the heap and wants to use it even after the parent has exited (!). Rather than doing even more hacks to get Go working, it seemed best to just use two intrinsics like in GCC. Patch mostly by Sanjoy Das. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139140 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03Revert r129875, XFAILing this test for arm, since the fix was reverted.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139058 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Pseudo CMOV instructions don't clobber EFLAGS.Jakob Stoklund Olesen
The explanation about a 0 argument being materialized as xor is no longer valid. Rematerialization will check if EFLAGS is live before clobbering it. The code produced by X86TargetLowering::EmitLoweredSelect does not clobber EFLAGS. This causes one less testb instruction to be generated in the cmov.ll test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Try to eliminate the use of the 'unwind' instruction.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Don't fast-isel for atomic load/store; some cases require extra handling ↵Eli Friedman
missing from fast-isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Better fix for this testcase. Update it to the new EH scheme entirely.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139039 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Update for new EH stuff. (I'm not sure if this is 100% correct.)Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Darwin wants ctors/dtors to be ordered the other way round to linux.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.Kalle Raiskila
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Revert r131152, r129796, r129761. This code is currently consideredDan Gohman
to be unreliable on platforms which require memcpy calls, and it is complicating broader legalize cleanups. It is hoped that these cleanups will make memcpy byval easier to implement in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Don't drop alignment info on local common symbols.Benjamin Kramer
- On COFF the .lcomm directive has an alignment argument. - On ELF we fall back to .local + .comm Based on a patch by NAKAMURA Takumi. Fixes PR9337, PR9483 and PR10128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138976 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01XFAIL this test on arm until the backend is fixed.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138955 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01This test depends on cmov being available.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Permit remat of partial register defs when it is safe.Jakob Stoklund Olesen
An instruction may define part of a register where the other bits are undefined. In that case, it is safe to rematerialize the instruction. For example: %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def> The extra <imp-def> operand indicates that the instruction does not read the other parts of the virtual register, so a remat is safe. This patch simply allows multiple def operands for the virtual register. It is MI->readsVirtualRegister() that determines if we depend on a previous value so remat is impossible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Fix vbroadcast matching logic to early unmatch if the node doesn't haveBruno Cardoso Lopes
only one use. Fix PR10825. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Prevent remat of partial register redefinitions.Jakob Stoklund Olesen
An instruction that redefines only part of a larger register can never be rematerialized since the virtual register value depends on the old value in other parts of the register. This was fixed for the inline spiller in r138794. This patch fixes the problem for all register allocators, and includes a small test case. <rdar://problem/10032939> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138944 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01PreRA scheduler should avoid cloning compares.Andrew Trick
Added canClobberReachingPhysRegUse() to handle a particular pattern in which a two-address instruction could be forced to interfere with EFLAGS, causing a compare to be unnecessarilly cloned. Fixes rdar://problem/5875261 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138924 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Remove old declare statements.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Update more tests to the new EH scheme.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Update more tests to the new EH scheme.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Revert r138894. This was failing on cmake-clang-i686-msvc10.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Update more tests to the new EH scheme.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138894 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; ↵Eli Friedman
implements 64-bit atomic load/store for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-3164-bit atomic cmpxchg for ARM.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138868 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Compress Repeated Byte OutputDavid Greene
Emit a repeated sequence of bytes using .zero. This saves an enormous amount of asm file space for certain programs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31This test requires sse, otherwise x87 ops will block tailcall optimizationBenjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138859 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31- Move all MOVSS and MOVSD patterns close to their definitionsBruno Cardoso Lopes
- Duplicate some store patterns to their AVX forms! - Catched a bug while restricting the patterns subtarget, fix it and update a testcase to check it properly git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138851 91177308-0d34-0410-b5e6-96231b3b80d8
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