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2011-10-18Fix incorrect check for sign-extended constant BUILD_VECTOR.Bob Wilson
<rdar://problem/10298332> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142371 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18Fix a DAG combiner assertion failure when constant folding BUILD_VECTORS.Bob Wilson
svn r139159 caused SelectionDAG::getConstant() to promote BUILD_VECTOR operands with illegal types, even before type legalization. For this testcase, that led to one BUILD_VECTOR with i16 operands and another with promoted i32 operands, which triggered the assertion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18PTX: Fix disabling of MAD instruction selectionJustin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142352 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18Add support for dynamic stack realignment when in thumb1 mode.Chad Rosier
rdar://10288916 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Add support for a new extension to the .file directive:Nick Lewycky
.file filenumber "directory" "filename" This removes one join+split of the directory+filename in MC internals. Because bitcode files have independent fields for directory and filenames in debug info, this patch may change the .o files written by existing .bc files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142300 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Add CHECKs and document PR11158.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142240 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17stabalize tests by specifying the exact sse levelNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142229 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17use FileCheck and not grep in new testsHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Clean the triple, add check lines.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142183 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Previously v2i32 vectors were legalized to v4i32. Now, they are legalized toNadav Rotem
v2i64. These tests do not check MMX nor zmoving into them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Test case for CanLowerReturn fix (r141981)Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Add PPC 440 scheduler and some associated tests (new files)Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add tripple and stabalize a few more tests.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142158 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add triple to tests.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142154 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16fix a typo in the testNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Enable element promotion type legalization by deafault.Nadav Rotem
Changed tests which assumed that vectors are legalized by widening them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Remove the the test which checks the saving of a vector of booleans into memory.Nadav Rotem
The decision was to pack the bits. Currently no codegen supports this. Currently, all of the bits in the vector are saved into the same address in memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142149 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there wasNadav Rotem
no pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142130 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Add missing correctness check to ARMTargetLowering::ReconstructShuffle. ↵Eli Friedman
Fixes PR11129. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Update live-in lists when splitting critical edges.Jakob Stoklund Olesen
Fixes PR10814. Patch by Jan Sjödin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141960 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Add X86 ANDN instruction. Including instruction selection.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 ↵Craig Topper
processor which is gcc's name for Haswell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Add value numbers when spilling dead defs.Jakob Stoklund Olesen
When spilling around an instruction with a dead def, remember to add a value number for the def. The missing value number wouldn't normally create problems since there would be an incoming live range as well. However, due to another bug we could spill a dead V_SET0 instruction which doesn't read any values. The missing value number caused an empty live range to be created which is dangerous since it doesn't interfere with anything. This fixes part of PR11125. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141923 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Force CPU type on test so it doesn't accidentally emit movbe instead of ↵Benjamin Kramer
bswap on Intel Atom CPUs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Mark 'branch indirect' instruction as an indirect branch.Kalle Raiskila
Not having it confused assembly printing of jumptables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13More closely follow libgcc, which has code after the `ret' instruction toBill Wendling
release the stack segment and reset the stack pointer. Place the code in its own MBB to make the verifier happy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141859 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Revert r141854 because it was causing failures:Bill Wendling
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101 --- Reverse-merging r141854 into '.': U test/MC/Disassembler/X86/x86-32.txt U test/MC/Disassembler/X86/simple-tests.txt D test/CodeGen/X86/bmi.ll U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86.td U lib/Target/X86/X86Subtarget.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141857 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Should not add instructions to a BB after a return instruction. The machine ↵Bill Wendling
instruction verifier doesn't like this, nor do I. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141856 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 ↵Craig Topper
processor which is gcc's name for Haswell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141854 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Also inflate register classes around inline asm.Jakob Stoklund Olesen
Now that MI->getRegClassConstraint() can also handle inline assembly, don't bail when recomputing the register class of a virtual register used by inline asm. This fixes PR11078. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12We need to verify that the machine instruction we're using as a replacement forBill Wendling
our current machine instruction defines a register with the same register class as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it would ICE because a tail call was expecting one register class but was given another. (The machine instruction verifier catches this situation.) <rdar://problem/10270968> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Fix -widen-vmovs liveness issues.Jakob Stoklund Olesen
When widening a copy, we are reading a larger register that may not be live. Use an <undef> flag to tell the register scavenger and machine code verifier that we know the value isn't defined. We now widen: %S6<def> = COPY %S4<kill>, %D3<imp-def> into: %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill> This also keeps the <kill> flag on %S4 so we don't inadvertently kill a live value in %S5. Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves the <undef> flag when converting VMOVD to VORR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Make this test more specific. There are 3 stats that matched "machine-licm".Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add a new wrapper node for a DILexicalBlock that encapsulates it and aEric Christopher
file. Since it should only be used when necessary propagate it through the backend code generation and tweak testcases accordingly. This helps with code like in clang's test/CodeGen/debug-info-line.c where we have multiple #line directives within a single lexical block and want to generate only a single block that contains each file change. Part of rdar://10246360 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141729 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Revert r141529. This is causing failures in the test-suite, like bigstack ↵Bill Wendling
and ReedSolomon. Boo... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141716 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add dominance check for the instruction being hoisted.Devang Patel
For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add support for legalization of vector SHL/SRA/SRL instructionsNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Test case for X86 LZCNT instruction selection.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141652 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Test simplification that Ana Pazos noticed.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141644 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11test/CodeGen/X86/movbe.ll: Give explicit -mtriple=x86_64-linux, to unbreak ↵NAKAMURA Takumi
win32 hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141640 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Test cases for 64-bit load and store instructions.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add testcase for PR11107.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141607 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Revert r141569 and r141576.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141594 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Reapply r141365 now that PR11107 is fixed.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. ↵Eli Friedman
Fixes PR11102. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10If loop header is also loop exiting block then it may not be safe to hoist ↵Devang Patel
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because theNadav Rotem
instruction set has no 64-bit SRA support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141570 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Add dominance check for the instruction being hoisted.Devang Patel
For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10X86: Add patterns for the movbe instruction (mov + bswap, only available on ↵Benjamin Kramer
atom) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141563 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame toBill Wendling
hang, and possibly SPEC/CINT2006/464_h264ref. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8
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