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2012-01-27Add r149110 back with a fix for when the vector and the int have the sameRafael Espindola
width. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149151 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27Revert r149110 and add a testcase that was crashing since that revision.Rafael Espindola
Unfortunately I also had to disable constant-pool-sharing.ll the code it tests has been updated to use the IL logic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149148 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27Unix line endingsMatt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149115 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27Rewrite instruction operands in AdjustCopiesBackFrom. Fixes PR11861.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149097 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26Handle call-clobbered ymm registers on Win64.Jakob Stoklund Olesen
The Win64 calling convention has xmm6-15 as callee-saved while still clobbering all ymm registers. Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the ymm registers, and mark that as call-clobbered. This allows live xmm registers across calls. This hack wouldn't be necessary with RegisterMask operands representing the call clobbers, but they are not quite operational yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149088 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26Replace the use of isPredicable() with isPredicated() inChad Rosier
MachineBasicBlock::canFallThrough(). We're interested in the state of the instruction (i.e., is this a barrier or not?), not if the instruction is predicable or not. rdar://10501092 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149070 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26Clear kill flags before propagating a copy.Jakob Stoklund Olesen
The live range of the source register may be extended when a redundant copy is eliminated. Make sure any kill flags between the two copies are cleared. This fixes PR11765. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149069 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26Fix for the following bug in AVX codegen for double-to-int conversions:Victor Umansky
. "fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode. . Currently for AVX mode for <4xdouble> and <8xdouble> the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode. . Consequently, the conversion produces incorrect numbers. The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode. As .fp_to_sint. DAG node operation is used only for lowering of "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows. The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149056 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25Improve sub-register def handling in ProcessImplicitDefs.Jakob Stoklund Olesen
This boils down to using MachineOperand::readsReg() more. This fixes PR11829 where a use ended up after the first def when lowering REG_SEQUENCE instructions involving IMPLICIT_DEFs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25Properly emit ctors / dtors with priorities into desired sectionsAnton Korobeynikov
and let linker handle the rest. This finally fixes PR5329 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148990 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25Modify MipsFrameLowering::emitPrologue and emitEpilogue.Akira Hatanaka
- Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit. - Change the types of variables so that they are sufficiently large to handle 64-bit pointers. - Emit instructions to set register $28 in a function prologue after instructions which store callee-saved registers have been emitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148917 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added. Akira Hatanaka
Add a test case to show fewer instructions are needed to load an immediate with the new way of loading immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148908 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Set correct <def,undef> flags when lowering REG_SEQUENCE.Jakob Stoklund Olesen
A REG_SEQUENCE instruction is lowered into a sequence of partial defs: %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0 %vreg7:ssub_1<def> = COPY %vreg2 %vreg7:ssub_2<def> = COPY %vreg2 %vreg7:ssub_3<def> = COPY %vreg2 The first def needs an <undef> flag to indicate it is the beginning of the live range, while the other defs are read-modify-write. Previously, we depended on LiveIntervalAnalysis to notice and fix the missing <def,undef>, but that solution was never robust, it was causing problems with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE instructions. This fixes PR11841. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148879 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Pattern for f32 to i64 conversion.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148869 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-2464-bit sign extension in register instructions.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148862 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24ZERO_EXTEND operation is optimized for AVX.Elena Demikhovsky
v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148803 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24An option to selectively enable part of ARM EHABI support.Evgeniy Stepanov
This change adds an new option --arm-enable-ehabi-descriptors that enables emitting unwinding descriptors. This provides a mode with a working backtrace() without the (currently broken) exception support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148800 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Revert r148686 (and r148694, a fix to it) due to a serious layeringChandler Carruth
violation -- MC cannot depend on CodeGen. Specifically, the MCTargetDesc component of each target is actually a subcomponent of the MC library. As such, it cannot depend on the target-independent code generator, because MC itself cannot depend on the target-independent code generator. This change moved a flag from the ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in ARMException.cpp, leaving behind an 'extern' to refer back to it. That layering order isn't viable givin the constraints outlined above. Commandline flags are designed to be static specifically to avoid these types of bugs. Fixing this is likely going to require some non-trivial refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148759 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23Fix PR11829. PostRA LICM was too aggressive.Jakob Stoklund Olesen
This fixes a typo in r148589. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23An option to selectively enable parts of ARM EHABI support.Evgeniy Stepanov
This change adds an new value to the --arm-enable-ehabi option that disables emitting unwinding descriptors. This mode gives a working backtrace() without the (currently broken) exception support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148686 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22Add fused multiple+add instructions from VFPv4.Anton Korobeynikov
Patch by Ana Pazos! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651>Bob Wilson
We have patterns for vector sext and zext operations but were missing anyext. Without those patterns, codegen will fail when the selection DAG has any_extend nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20VST2 four-register w/ update pseudos for fixed/register update.Jim Grosbach
rdar://10724489 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148560 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20Add support for selecting 256-bit PALIGNR.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148532 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20Remove a low-quality test which was failing on Windows; ↵Eli Friedman
test/CodeGen/X86/sret.ll is a better test for the relevant behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148526 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148513 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.Evgeniy Stepanov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148473 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19Space after punctuation.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148451 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19Add a TargetOption for disabling tail calls.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148442 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Fix a bug in the type-legalization of vector integers. When we bitcast one ↵Nadav Rotem
vector type to another, we must not bitcast the result if one type is widened while the other is promoted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148383 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148337 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Fix 11769.Nadav Rotem
In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner. However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148298 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16AggressiveAntiDepBreaker needs to skip debug values because a debug value ↵Hal Finkel
does not have a corresponding SUnit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148260 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16Make sure the non-SSE lowering for fences correctly clobbers EFLAGS. PR11768.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148240 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-15[AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.Nadav Rotem
We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148225 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-15Relax the FileCheck assertion a bit -- all we really care about is thatChandler Carruth
we're loading from the global array, not how it is spelled in the asm. This should fix the MSVC bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148214 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-15FileCheck-ize a test, make it more specific to directly test the shiftChandler Carruth
removal desired. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148213 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-14After r147827 and r147902, it's now possible for unallocatable registers to beEvan Cheng
live across BBs before register allocation. This miscompiled 197.parser when a cmp + b are optimized to a cbnz instruction even though the CPSR def is live-in a successor. cbnz r6, LBB89_12 ... LBB89_12: ble LBB89_1 The fix consists of two parts. 1) Teach LiveVariables that some unallocatable registers might be liveouts so don't mark their last use as kill if they are. 2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional branch does not kill CPSR. rdar://10676853 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148168 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-14Cleanup test case by adding checks for test names.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-14Add a test showing how the Leh_func_endN symbol is used.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148161 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13test/CodeGen/ARM/test-sharedidx.ll: Fix for -Asserts.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match ↵Craig Topper
v4i64 and v8i32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148106 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13DAGCombine's logic for forming pre- and post- indexed loads / stores were beingEvan Cheng
overly conservative. It was concerned about cases where it would prohibit folding simple [r, c] addressing modes. e.g. ldr r0, [r2] ldr r1, [r2, #4] => ldr r0, [r2], #4 ldr r1, [r2] Change the logic to look for such cases which allows it to form indexed memory ops more aggressively. rdar://10674430 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failureElena Demikhovsky
lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&& "Op 1 of shuffle should not be undef"' failed. Added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148044 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Add error-reporting tests for platforms that don't support segmented stacks.Rafael Espindola
Patch by Brian Anderson. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148042 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Support segmented stacks on 64-bit FreeBSD.Rafael Espindola
This patch uses tcb_spare field in the tcb structure to store info. Patch by Jyun-Yan You. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148041 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Support segmented stacks on win32.Rafael Espindola
Uses the pvArbitrary slot of the TIB, which is reserved for applications. We only support frames with a static size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148040 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Fix a bug in the AVX 256-bit shuffle code in cases where the splat element ↵Nadav Rotem
is on the boundary of two 128-bit vectors. The attached testcase was stuck in an endless loop. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12X86: Generalize the x << (y & const) optimization to also catch masks with ↵Benjamin Kramer
more set bits set than 31 or 63. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148024 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11On AVX, we can load v8i32 at a time. The bug happens when two uneven loads ↵Nadav Rotem
are used. When we load the v12i32 type, the GenWidenVectorLoads method generates two loads: v8i32 and v4i32 and attempts to use CONCAT_VECTORS to join them. In this fix I concat undef values to widen the smaller value. The test "widen_load-2.ll" also exposes this bug on AVX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147964 91177308-0d34-0410-b5e6-96231b3b80d8
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