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2012-02-18Testcase for the previous commit.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150852 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17It turns out that putting an 8-byte symbol in a 4-byte section makes Solaris ↵David Chisnall
ld sulk. GNU ld is perfectly happy with it, which is worrying for a whole other set of reasons... Thanks to Anton, Duncan and Rafael for helping me track this down. Pointy hat to Rafael for introducing the bug in the first place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150811 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17[fast-isel] Add support for returning non-legal types with no sign- or zero-Chad Rosier
entend flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150774 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16Use –mcpu=generic, so that the test will not fail when run on an Intel AtomBill Wendling
processor, due to the Atom scheduler producing an instruction sequence that is different from that which is expected. Patch by Michael Spencer! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150736 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16Disable machine copy propagation for now. It's known to be buggy (PR11940) ↵Benjamin Kramer
and introduces subtle miscompiles in many places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150703 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16Replace all instances of dg.exp file with lit.local.cfg, since all tests are ↵Eli Bendersky
run with LIT now and now Dejagnu. dg.exp is no longer needed. Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Add a test for generating Objective-C metadata from module flags.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150635 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Stop custom lowering forr x86 DEC64m from happening if the load in the ↵Pete Cooper
lowered sequence has more than 1 user git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Tighten physical register invariants: Allocatable physical registers canLang Hames
only be live in to a block if it is the function entry point or a landing pad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150494 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Fix PR12000. Some vector operations may use scalar operands with typesNadav Rotem
that are greater than the vector element type. For example BUILD_VECTOR of type <1 x i1> with a constant i8 operand. This patch fixes the assertion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150477 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant ↵Nadav Rotem
generate a shuffle node from two vectors of different types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150383 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Revert accidental commit of a pruned testcase from r150360.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150361 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Update CanXFormVExtractWithShuffleIntoLoad to ensure bitcasts of loads only ↵Craig Topper
have one use. Matches DAGCombiner and prevents vector_shuffles from reaching isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150360 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Fixed bug when custom lowering DEC64m on x86.Pete Cooper
If the DEC node had more than one user, it was doing this lowering but leaving the original DEC node around and so decrementing twice. Fixes PR11964. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150356 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12This patch addresses the problem of poor code generation for the zextNadav Rotem
v8i8 -> v8i32 on AVX machines. The codegen often scalarizes ANY_EXTEND nodes. The DAGCombiner has two optimizations that can mitigate the problem. First, if all of the operands of a BUILD_VECTOR node are extracted from an ZEXT/ANYEXT nodes, then it is possible to create a new simplified BUILD_VECTOR which uses UNDEFS/ZERO values to eliminate the scalar ZEXT/ANYEXT nodes. Second, another dag combine optimization lowers BUILD_VECTOR into a shuffle vector instruction. In the case of zext v8i8->v8i32 on AVX, a value in an XMM register is to be shuffled into a wide YMM register. This patch modifes the second optimization and allows the creation of shuffle vectors even when the newly generated vector and the original vector from which we extract the values are of different types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Add support for implicit TLS model used with MS VC runtime.Anton Korobeynikov
Patch by Kai Nacke! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150307 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick
Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09test/CodeGen/X86/atom-lea-sp.ll: Add explicit -mtriple=i686-linux.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150151 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08Commit Andy Zhang's test for the lea patch.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08Fixed a bug in printing "cmp" pseudo ops.Elena Demikhovsky
> This IR code > %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 14) > fails with assertion: > > llc: X86ATTInstPrinter.cpp:62: void llvm::X86ATTInstPrinter::printSSECC(const llvm::MCInst*, unsigned int, llvm::raw_ostream&): Assertion `0 && "Invalid ssecc argument!"' failed. > 0 llc 0x0000000001355803 > 1 llc 0x0000000001355dc9 > 2 libpthread.so.0 0x00007f79a30575d0 > 3 libc.so.6 0x00007f79a23a1945 gsignal + 53 > 4 libc.so.6 0x00007f79a23a2f21 abort + 385 > 5 libc.so.6 0x00007f79a239a810 __assert_fail + 240 > 6 llc 0x00000000011858d5 llvm::X86ATTInstPrinter::printSSECC(llvm::MCInst const*, unsigned int, llvm::raw_ostream&) + 119 I added the full testing for all possible pseudo-ops of cmp. I extended X86AsmPrinter.cpp and X86IntelInstPrinter.cpp. You'l also see lines alignments (unrelated to this fix) in X86IselLowering.cpp from my previous check-in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150068 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08[fast-isel] Add support for SUBs with non-legal types.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150047 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08Add comment to test case.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150046 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08[fast-isel] Add support for ORs with non-legal types.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07[fast-isel] Add support for indirect branches.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07Add instruction selection for 256-bit VPSHUFD and 128-bit VPERMILPS/VPERMILPD.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149968 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06[fast-isel] Add support for ADDs with non-legal types.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149934 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05Testcase for commit 149833 (use of an uninitialized variable noticedDuncan Sands
by GCC). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149840 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05Testing vector code without sse doesn't make much sense.Benjamin Kramer
Should bring arm and ppc testers back to life (they default to -mcpu=generic) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149821 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05Add a test for the miscompilation my recent ConstantDataArray patches ↵Chris Lattner
introduced, to make sure we don't regress on it in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149803 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05Remove most of the intrinsics for XOP VPCMOV instruction. They all aliased ↵Craig Topper
to the same instruction with different types. This would be better accomplished with casts in the not yet created xopintrin.h header file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149795 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-04[fast-isel] HandlePHINodesInSuccessorBlocks() can promite i8 and i16 types too.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149730 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03[fast-isel] Add support for FPToUI. Also add test cases for FPToSI.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149706 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03[fast-isel] Add support for selecting UIToFP.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149704 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03The type-legalizer often scalarizes code. One of the common patterns is ↵Nadav Rotem
extract-and-truncate. In this patch we optimize this pattern and convert the sequence into extract op of a narrow type. This allows the BUILD_VECTOR dag optimizations to construct efficient shuffle operations in many cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149692 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which isAkira Hatanaka
needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149668 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02Unix line endingsMatt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149615 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02Move test/CodeGen/Generic/2012-02-01-CoalescerBug.ll to CodeGen/ARM, for ↵NAKAMURA Takumi
now. It requires TARGETS=arm. I cannot reproduce a fixed issue with other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02Optimization for SIGN_EXTEND operation on AVX.Elena Demikhovsky
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32 extensions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149600 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02Set EFLAGS correctly in EmitLoweredSelect on X86.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149597 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02PR11868. The previous loop in LiveIntervals::join would sometimes fall over ifLang Hames
more than two adjacent ranges needed to be merged. The new version should be able to handle an arbitrary sequence of adjancent ranges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149588 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Instruction scheduling itinerary for Intel Atom.Andrew Trick
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Avoid creating an extract element to an illegal type after LegalizeTypes has ↵Mon P Wang
run. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149548 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01VLIW specific scheduler framework that utilizes deterministic finite ↵Andrew Trick
automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149547 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01test/CodeGen/X86/avx-minmax.ll: Relax expressions for Win32 targets. YMM ↵NAKAMURA Takumi
arguments are passed as indirect on Win32 x64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149505 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Passing AVX 256-bit structures in Win64 was wrong.Elena Demikhovsky
Fixed Win64 calling conventions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149494 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Optimization for "truncate" operation on AVX.Elena Demikhovsky
Truncating v4i64 -> v4i32 and v8i32 -> v8i16 may be done with set of shuffles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149485 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Remove pcmpgt/pcmpeq intrinsics as clang is not using them.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149367 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Remove all references to the old EH.Bill Wendling
There was always the current EH. -- Ministry of Truth git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149335 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30Chris's constant data sequence refactoring actually enabled printingChandler Carruth
vectors of all one bits to be printed more cleverly in the AsmPrinter. Unfortunately, the byte value for all one bits is the same with -fsigned-char as the error return of '-1'. Force this to be the unsigned byte value when returning it to avoid this problem, and update the test case for the shiny new behavior. Yay for building LLVM and Clang with -funsigned-char. Chris, please review, and let me know if there is any reason to not desire this change. It seems good on the surface, and certainly intended based on the code written. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30Fix pattern for memory form of PSHUFD for use with FP vectors to remove ↵Craig Topper
bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149232 91177308-0d34-0410-b5e6-96231b3b80d8
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