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2012-04-25Try to fix llvm-arm-linux builder with -mcpu.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155589 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Trivial change to make the test use -mcpu=generic so as to avoidPreston Gurd
a failure if run on an Intel Atom with post RA instruction scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Do not use $gp as a dedicated global register if the target ABI is not O32. Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155522 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Fix the testcase. We do expect two vblendw on XMMs.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155477 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Add a testcase for 155440Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155475 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24MachineBasicBlock::SplitCriticalEdge() should follow LLVM IR variant and ↵Evan Cheng
refuse to break edge to EH landing pad. rdar://11300144 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155470 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24AVX: We lower VECTOR_SHUFFLE and BUILD_VECTOR nodes into vbroadcast instructionsNadav Rotem
using the pattern (vbroadcast (i32load src)). In some cases, after we generate this pattern new users are added to the load node, which prevent the selection of the blend pattern. This commit provides fallback patterns which perform in-vector broadcast (using in-vector vbroadcast in AVX2 and pshufd on AVX1). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155437 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Optimize the vector UINT_TO_FP, SINT_TO_FP and FP_TO_SINT operations where ↵Nadav Rotem
the integer type is i8 (commonly used in graphics). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155397 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd
on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information. When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to run the RegisterScavenging code in the BranchFolding pass. This patch makes sure that the register scavenging code is invoked in the X86 subtarget only when post-RA scheduling is being done. Post RA scheduling in the X86 subtarget is only done for Atom. This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular. The patch adds and invokes the new function trackLivenessAfterRegAlloc() instead of using the existing requiresRegisterScavenging(). It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of requiresRegisterScavenging(). It changes the all the targets that implemented requiresRegisterScavenging() to also implement trackLivenessAfterRegAlloc(). It adds an assertion in the Post RA scheduler to make sure that post RA liveness information is available when it is needed. It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order to avoid running into the added assertion. Finally, this patch restores the use of anti-dependency checking (which was turned off temporarily for the 3.1 release) for Intel Atom in the Post RA scheduler. Patch by Andy Zhang! Thanks to Jakob and Anton for their reviews. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Revert r155365, r155366, and r155367. All three of these have regressionChandler Carruth
test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155372 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Hexagon V5 (floating point) support.Sirish Pande
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155367 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Support for Hexagon architectural feature, new value jump.Sirish Pande
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Support for Hexagon VLIW Packetizer.Sirish Pande
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155365 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-22cleaned line endings in the newly added test fileElena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155315 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-22ZERO_EXTEND/SIGN_EXTEND/TRUNCATE optimization for AVX2Elena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155309 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-21Teach getVectorTypeBreakdown about promotion of vectors in addition to ↵Nadav Rotem
widening of vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155296 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20Fix PR12599.Jakob Stoklund Olesen
The X86 target is editing the selection DAG while isel is selecting nodes following a topological ordering. When the DAG hacking triggers CSE, nodes can be deleted and bad things happen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155257 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-19Test for the the problem with xors being changed into andsJoel Jones
when the set bits aren't the same for both args of the xor. This transformation is in the function TargetLowering::SimplifyDemandedBits in the file lib/CodeGen/SelectionDAG/TargetLowering.cpp. I have tested this test using a previous version of llc which the defect and the a version of llc which does not. I got the expected fail and pass, respectively. This test goes with rdar://11195364 and the check in with the fix: svn r154955 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155156 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Move win32 SimplifyLibcall test under TransformsJoe Groff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154967 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17fix pr12559: mark unavailable win32 math libcallsJoe Groff
also fix SimplifyLibCalls to use TLI rather than compile-time conditionals to enable optimizations on floor, ceil, round, rint, and nearbyint git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17Force cmov on test so block placement doesn't shuffle the code around.Benjamin Kramer
This made the test fail with -mcpu=generic (when building on a non-x86 host). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154926 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17Fix bad EXTRACT_SUBREG in instruction selection for extending-loads on NEON.James Molloy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154915 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17Test cases that assume layout should use -disable-code-place.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154908 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17temporarily XFAIL this test until post RAPreston Gurd
live-ins is properly enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154882 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16Disable the atom scheduling test after r154874 broke it.Chandler Carruth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16Relax this test a touch to cope with different assembly variants.Chandler Carruth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154870 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16Fix updateTerminator to be resiliant to degenerate terminators whereChandler Carruth
both fallthrough and a conditional branch target the same successor. Gracefully delete the conditional branch and introduce any unconditional branch needed to reach the actual successor. This fixes memory corruption in 2009-06-15-RegScavengerAssert.ll and possibly other tests. Also, while I'm here fix a latent bug I spotted by inspection. I never applied the same fundamental fix to this fallthrough successor finding logic that I did to the logic used when there are no conditional branches. As a consequence it would have selected landing pads had they be aligned in just the right way here. I don't have a test case as I spotted this by inspection, and the previous time I found this required have of TableGen's source code to produce it. =/ I hate backend bugs. ;] Thanks to Jim Grosbach for helping me reason through this and reviewing the fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154867 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16FileCheckize these tests.Jakob Stoklund Olesen
Add an extra test to ldr_post with an immediate increment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154859 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16Disable code placement for this test.Jakob Stoklund Olesen
It makes it less sensitive to small changes in heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154857 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16Fix incorrect atomics codegen introduced in r154705, and extend test to ↵Richard Smith
catch it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154845 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16Move to X86 directory because this fails on non-X86 platforms.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154825 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16Flip the new block-placement pass to be on by default.Chandler Carruth
This is mostly to test the waters. I'd like to get results from FNT build bots and other bots running on non-x86 platforms. This feature has been pretty heavily tested over the last few months by me, and it fixes several of the execution time regressions caused by the inlining work by preventing inlining decisions from radically impacting block layout. I've seen very large improvements in yacr2 and ackermann benchmarks, along with the expected noise across all of the benchmark suite whenever code layout changes. I've analyzed all of the regressions and fixed them, or found them to be impossible to fix. See my email to llvmdev for more details. I'd like for this to be in 3.1 as it complements the inliner changes, but if any failures are showing up or anyone has concerns, it is just a flag flip and so can be easily turned off. I'm switching it on tonight to try and get at least one run through various folks' performance suites in case SPEC or something else has serious issues with it. I'll watch bots and revert if anything shows up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16Remove an overly brittle test. This test will no longer be interestingChandler Carruth
once we start changing the block layout, so just nuke it. If anyone has ideas about how to craft a code layout agnostic form of the test please let me know. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154815 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16Add a somewhat hacky heuristic to do something different from whole-loopChandler Carruth
rotation. When there is a loop backedge which is an unconditional branch, we will end up with a branch somewhere no matter what. Try placing this backedge in a fallthrough position above the loop header as that will definitely remove at least one branch from the loop iteration, where whole loop rotation may not. I haven't seen any benchmarks where this is important but loop-blocks.ll tests for it, and so this will be covered when I flip the default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154812 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16Tweak the loop rotation logic to check whether the loop is naturallyChandler Carruth
laid out in a form with a fallthrough into the header and a fallthrough out of the bottom. In that case, leave the loop alone because any rotation will introduce unnecessary branches. If either side looks like it will require an explicit branch, then the rotation won't add any, do it to ensure the branch occurs outside of the loop (if possible) and maximize the benefit of the fallthrough in the bottom. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154806 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16Remove dead SD nodes after the combining pass. Fixes PR12201.Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154786 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16Rewrite how machine block placement handles loop rotation.Chandler Carruth
This is a complex change that resulted from a great deal of experimentation with several different benchmarks. The one which proved the most useful is included as a test case, but I don't know that it captures all of the relevant changes, as I didn't have specific regression tests for each, they were more the result of reasoning about what the old algorithm would possibly do wrong. I'm also failing at the moment to craft more targeted regression tests for these changes, if anyone has ideas, it would be welcome. The first big thing broken with the old algorithm is the idea that we can take a basic block which has a loop-exiting successor and a looping successor and use the looping successor as the layout top in order to get that particular block to be the bottom of the loop after layout. This happens to work in many cases, but not in all. The second big thing broken was that we didn't try to select the exit which fell into the nearest enclosing loop (to which we exit at all). As a consequence, even if the rotation worked perfectly, it would result in one of two bad layouts. Either the bottom of the loop would get fallthrough, skipping across a nearer enclosing loop and thereby making it discontiguous, or it would be forced to take an explicit jump over the nearest enclosing loop to earch its successor. The point of the rotation is to get fallthrough, so we need it to fallthrough to the nearest loop it can. The fix to the first issue is to actually layout the loop from the loop header, and then rotate the loop such that the correct exiting edge can be a fallthrough edge. This is actually much easier than I anticipated because we can handle all the hard parts of finding a viable rotation before we do the layout. We just store that, and then rotate after layout is finished. No inner loops get split across the post-rotation backedge because we check for them when selecting the rotation. That fix exposed a latent problem with our exitting block selection -- we should allow the backedge to point into the middle of some inner-loop chain as there is no real penalty to it, the whole point is that it *won't* be a fallthrough edge. This may have blocked the rotation at all in some cases, I have no idea and no test case as I've never seen it in practice, it was just noticed by inspection. Finally, all of these fixes, and studying the loops they produce, highlighted another problem: in rotating loops like this, we sometimes fail to align the destination of these backwards jumping edges. Fix this by actually walking the backwards edges rather than relying on loopinfo. This fixes regressions on heapsort if block placement is enabled as well as lots of other cases where the previous logic would introduce an abundance of unnecessary branches into the execution. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154783 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-15Remove AVX2 vpermq and vpermpd intrinsics. These can now be handled with ↵Craig Topper
normal shuffle vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-15Fix PR12529. The Vxx family of instructions are only supported by AVX.Nadav Rotem
Use non-vex instructions for SSE4. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154770 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-15When emulating vselect using OR/AND/XOR make sure to bitcast the result back ↵Nadav Rotem
to the original type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-15Added VPERM optimization for AVX2 shufflesElena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154761 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-13Fix X86 codegen for 'atomicrmw nand' to generate *x = ~(*x & y), not *x = ↵Richard Smith
~*x & y. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154705 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-13On Darwin targets, only use vfma etc. if the source use fma() intrinsic ↵Evan Cheng
explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154689 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-12Disable Hexagon test temporarily.Sirish Pande
There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA). This assert needs to addressed for post RA scheduler. Until that assert is addressed, any passes that uses post ra scheduler will fail. So, I am temporarily disabling the hexagon tests until that fix is in. The assert is as follows: assert(!MI->isTerminator() && !MI->isLabel() && "Cannot schedule terminators or labels!"); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154617 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-12Fix 128-bit ptest intrinsics to take v2i64 instead of v4f32 since these are ↵Craig Topper
integer instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154580 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11Revert changes that were accidentally committed.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154563 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11Fix string that is being checked.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154547 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user,Akira Hatanaka
otherwise expand FNEG during legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154546 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user.Akira Hatanaka
Invalid operation is signaled if the operand of these instructions is NaN. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154545 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11Fix bugs in lowering of FCOPYSIGN nodes.Akira Hatanaka
- FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154540 91177308-0d34-0410-b5e6-96231b3b80d8
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